Double-Encapsulated Power Semiconductor Module for Thermomechanical Stress Reduction
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Solution Overview
Problem
Power semiconductor modules face thermomechanical stress due to thick encapsulation layers with high coefficients of thermal expansion, which can damage semiconductor chips and bond wires, especially when operating at high temperatures.
Innovation Solution
A power semiconductor module design featuring a dielectric silicone rubber first encapsulation with a higher modulus of elasticity than a silicone foam second encapsulation, where the first encapsulation is in physical contact with both the substrate and the second encapsulation, and the semiconductor chip is embedded between them, reducing thermomechanical stress and maintaining dielectric strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick encapsulation layer is used to provide sufficient dielectric strength and coverage, then electrical insulation is improved, but thermomechanical stress on semiconductor chips and bond wires increases
Solution Approach 1:
The encapsulation is divided into two distinct layers: a first encapsulation layer in direct contact with the semiconductor chip and substrate, and a second encapsulation layer covering the first layer. This segmentation allows each layer to have optimized properties - the first layer provides stress buffering with lower modulus of elasticity, while the second layer provides dielectric strength with higher thickness
Solution Approach 2:
The patent uses composite material structure with two different encapsulation materials having different mechanical properties. The first encapsulation material has a lower modulus of elasticity to reduce stress, while the second encapsulation material can have different properties for external protection. This composite approach allows simultaneous achievement of stress reduction and sufficient dielectric strength
2Reliability
If the encapsulation material has high dielectric strength to withstand high voltages, then electrical insulation is improved, but the material becomes harder and exerts more stress on chip connections
Solution Approach 1:
Different regions of the encapsulation structure have different material properties optimized for their specific functions. The first encapsulation layer in contact with the chip has lower modulus of elasticity to protect connections, while the second encapsulation layer has properties optimized for external dielectric strength and voltage withstanding capability
3Reliability
If the encapsulation layer is thick to cover all terminals and provide insulation, then electrical safety is improved, but the volume and pressure exerted on internal components increases
Solution Approach 1:
The thick encapsulation requirement is satisfied through segmentation into two layers. The second encapsulation layer provides the necessary thickness for electrical safety and voltage withstanding, while the first encapsulation layer provides a compliant interface that reduces pressure transmission to internal components through its lower modulus of elasticity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The module effectively minimizes thermomechanical stress on semiconductor chips and bond wires while maintaining high dielectric strength, preventing damage such as chip cracks and bond wire lifting, and avoiding bubble formation that reduces dielectric strength.
Implementation Method 1
a first coefficient of thermal expansion of the first encapsulation material is different from a second coefficient of thermal expansion of the second encapsulation material
Implementation Method 2
a first modulus of elasticity of the first encapsulation material is different from a second modulus of elasticity of the second encapsulation material
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 3A~3C
AI summary
One aspect relates to a power semiconductor module. The module includes a module housing (6), a substrate, and a semiconductor chip (1) that is attached to the substrate (2). The semiconductor chip (1) is disposed in the module housing (6). A dielectric first encapsulation (51) is disposed in the module housing (6), in physical contact with both the semiconductor chip (1) and the substrate (2) and has a first modulus of elasticity. A dielectric second encapsulation (52) is disposed in the module housing (6) and has a second modulus of elasticity. The first encapsulation (51) is a polymer and disposed between the substrate (2) and the second encapsulation (52). The semiconductor chip (1) is disposed between the first encapsulation (51) and the substrate (2). Further, the first modulus of elasticity is greater than the second modulus of elasticity.