Double Etch Stop Via Structure for Seam-Free Metal Filling
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in achieving high integration, reduced size, and low power consumption while ensuring reliable wiring connections as spacing between circuit components decreases, leading to issues like incomplete metal filling and seam defects in narrow openings.
Innovation Solution
A semiconductor device design incorporating a double etch stop layer with a lower and upper etch stop pattern, combined with a rounded via hole structure, facilitates reliable via and wiring connections by preventing incomplete metal filling and seam formation, even at critical dimensions below 15 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between circuit components is reduced to achieve high integration and reduced size, then device integration and miniaturization are improved, but wiring connection reliability deteriorates due to incomplete metal filling and seam defects
Solution Approach 1:
The patent divides the single etch stop layer into two separate etch stop layers (first etch stop layer and second etch stop layer) with different etching selectivities. This segmentation allows independent optimization of each layer's thickness and material properties, enabling precise control over the via hole formation process at critical dimensions while maintaining wiring connection reliability despite reduced spacing between circuit components.
Solution Approach 2:
The patent changes the etching selectivity parameter by using different materials for the first and second etch stop layers. The first etch stop layer has higher etching selectivity relative to the interlayer insulating layer than the second etch stop layer, allowing differential etching rates that prevent incomplete metal filling and seam defects even when via hole dimensions are reduced for high integration.
2Volume of moving object
If the via hole opening is narrowed to reduce device size, then device miniaturization is improved, but metal filling completeness deteriorates leading to seam defects
Solution Approach 1:
The patent performs preliminary etching through the first etch stop layer before completing the via hole formation. The first etch stop layer with higher etching selectivity acts as a temporary barrier that allows controlled preliminary etching, ensuring proper via hole shape and dimensions are achieved before final metal filling, thereby preventing seam defects even in narrowed openings.
Solution Approach 2:
The first etch stop layer serves as an intermediary layer between the interlayer insulating layer and the second etch stop layer. Its higher etching selectivity mediates the etching process by providing a controlled resistance to etching, which helps maintain via hole opening quality and prevents incomplete metal filling while allowing device miniaturization.
Data Source
AI summary
A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.