Double Exposure Semiconductor Process for Polysilicon Interconnect Precision
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Solution Overview
Problem
Conventional microlithographic processes face challenges in achieving precise control over feature sizes in semiconductor manufacturing, particularly in reducing certain critical pattern dimensions while maintaining acceptable process margins, especially at nanometer scales.
Innovation Solution
A double exposure semiconductor process is employed, where a first exposure and development are followed by trimming to achieve initial dimensions, and a second exposure without trimming is used to define device features, allowing for controlled hard mask and polysilicon etching to maintain critical dimensions and prevent undesirable reductions in feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single exposure process is used to define nanometer features, then the process is simple and fast, but it is challenging to achieve the required feature size precision and process margins
Solution Approach 1:
The patent divides the single exposure process into two separate exposure steps: a first exposure that defines oversized features (e.g., 80 nm) followed by a trimming process, and a second exposure that defines the final critical features (e.g., 50 nm) without trimming. This segmentation allows each exposure to be optimized independently, achieving both precision for critical features and efficiency for non-critical features.
2Manufacturing precision
If photoresist trimming is applied to reduce feature sizes to achieve tighter dimensions, then manufacturing precision is improved, but other critical feature patterns are also reduced in size causing poly-to-contact and field poly line resistance to exceed acceptable margins
Solution Approach 1:
The patent applies trimming selectively only to regions containing non-critical features (such as interconnect lines) while leaving regions containing critical electrical features (such as poly-to-contact enclosures and field poly) untrimmed. This local differentiation allows precise control over where dimension reduction occurs, maintaining electrical reliability while achieving tighter dimensions where needed.
Solution Approach 2:
The first exposure and trimming process is performed in advance to define interconnect features at relaxed dimensions, while the second exposure subsequently defines critical features at their final precise dimensions without trimming. This preliminary action allows the critical features to be established after trimming has already occurred, preventing their dimensions from being reduced.
3Area of stationary object
If conventional single exposure processes are used, then device spacing can be reduced to achieve higher integration, but control over critical pattern dimensions deteriorates
Solution Approach 1:
By separating the definition of interconnect features (first exposure with trimming) from critical feature definition (second exposure without trimming), the patent enables tighter device spacing while maintaining precise control over critical pattern dimensions. The two-exposure approach allows overlapping regions to be processed differently based on their functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables tighter control over critical pattern dimensions and device spacing, eliminating undesirable reductions and enhancing process margins, thereby improving the precision and yield of nanometer-scale semiconductor features.
Implementation Method 1
a layer of photoresist material is deposited above the hard mask layer by spin coating a uniform layer of photoresist over the entire surface of the starting material. The photoresist layer may then be selectively exposed to geometrically defined patterns of radiation, such as ultraviolet (UV) light
Implementation Method 2
An oxygen plasma trimming process may also be employed to remove quantities of unwanted photoresist that remain after the photoresist development process is complete
Implementation Method 3
After exposure, the photoresist is subjected to a development process that converts the latent image in the photoresist into the final image
Implementation Method 4
The final image serves as the mask in subsequent subtractive, e.g., etching, or additive, e.g., ion implantation, steps to selectively remove, or deposit, material from/to the starting material
Data Source
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AI summary
A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.