Asymmetric Double-Gate Vertical Channel Structure for GIDL Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and enhancing performance due to limitations in device structure, particularly in controlling the thickness or diameter of vertical nanosheets or nanowires and reducing gate-induced drain leakage (GIDL).
Innovation Solution
A semiconductor device with a double-gate structure is developed, featuring a vertical channel portion on a substrate with source/drain portions at both ends and offset gate stacks on opposite sides, where the distance between the gate edges and source/drain portions are carefully controlled to suppress GIDL. The device is manufactured using a method involving epitaxial growth and selective etching to form the channel and gate stacks, allowing for precise control of gate lengths and channel thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical nanosheet or nanowire device structure is used, then integration density can be increased, but it becomes difficult to control the thickness or diameter of the nanosheet or nanowire
Solution Approach 1:
The device structure is divided into multiple horizontal layers (first material layer, second material layer, third material layer) with the channel formation region segmented between them. This segmentation allows independent control of each layer's thickness and composition, enabling precise control of the vertical channel dimensions while maintaining high integration density through the vertical stacking architecture.
2Device complexity
If conventional single-gate structures are used, then device structure is simple, but gate-induced drain leakage (GIDL) cannot be effectively reduced
Solution Approach 1:
The patent implements an asymmetric double-gate structure where the first gate stack and second gate stack are positioned at different vertical locations relative to the channel formation region. The first gate stack is associated with the first material layer while the second gate stack is associated with the third material layer, creating unequal gate-to-channel distances that enable independent optimization of electron transport and GIDL suppression.
Solution Approach 2:
The invention transitions from a conventional planar single-gate structure to a vertical double-gate structure, adding the vertical dimension to gate control. By positioning gate stacks at different vertical levels above and below the channel formation region, the patent achieves three-dimensional electrostatic control that effectively suppresses GIDL while maintaining structural simplicity.
3Ease of manufacture
If photolithography and etching processes are used for vertical nanosheet devices, then manufacturing is feasible, but process fluctuations make it difficult to control nanosheet thickness or nanowire diameter
Solution Approach 1:
The patent forms the horizontal material layers (first, second, and third material layers) with precisely controlled thicknesses before creating the vertical channel structure. This preliminary formation of layered materials with atomic-level thickness control provides a template that guides subsequent channel formation, ensuring precise thickness control without relying on photolithography or etching for the critical dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double-gate structure effectively suppresses GIDL and improves control over channel size and gate length, enhancing device performance and integration density.
Implementation Method 1
forming a channel layer in the first recess portion
Implementation Method 2
removing the second material layer through the opening, and forming a second gate stack in a space released due to a removal of the second material layer
Data Source
AI summary
A semiconductor device having a double-gate structure and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a first gate stack and a second gate stack on opposite sides of the channel portion in a first direction lateral to the substrate. A distance between an upper edge and/or a lower edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion may be less than a distance between a corresponding upper edge and/or a corresponding lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion.