Double-Gate Carbon Nanotube Transistor for Short-Channel Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in transistor scaling due to unwanted short channel effects such as drain-induced barrier lowering and large subthreshold swing, which are exacerbated by the reduction in transistor size, and traditional 3D bulk crystal channel materials suffer from carrier scattering and increased threshold voltage variations.
Innovation Solution
A double-gate carbon nanotube transistor is fabricated by forming carbon nanotubes over a dielectric layer, suspending them, and encircling them with a gate dielectric and electrode, reducing short-channel effects through a specific process flow that includes forming a dummy gate stack, removing it, and creating a replacement gate stack with a high-k dielectric and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase density, then productivity is improved, but short channel effects worsen
Solution Approach 1:
The patent transitions from conventional planar single-gate transistors to vertically stacked double-gate transistors, utilizing the third dimension (vertical stacking) to increase transistor density while maintaining effective gate control over the channel through dual gates positioned above and below the channel region
Solution Approach 2:
The channel region is divided into two separately controlled segments by introducing two independent gates (first gate and second gate) positioned on opposite sides of the channel, allowing independent voltage control of each gate to mitigate short channel effects while maintaining high density
2Reliability
If channel body thickness is reduced to mitigate short channel effects, then reliability is improved, but manufacturing precision worsens
Solution Approach 1:
The patent changes the gating parameter from single-gate to double-gate configuration, where two gates with independently controllable voltages provide superior electrostatic control over the channel, reducing sensitivity to thickness variations and suppressing short channel effects without requiring extremely precise thickness control
3Manufacturing precision
If 3D bulk crystal channel materials are used, then manufacturing precision is maintained, but reliability worsens
Solution Approach 1:
The patent employs a composite channel structure consisting of semiconductor nanowires or nanoribbons (such as SiGe, GaAs, or InP) suspended between gates, combining the benefits of crystalline semiconductor materials with a geometry that eliminates carrier scattering at surfaces while maintaining fabrication compatibility
Data Source
AI summary
A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.