Double-Gate FeFET Structure for Bipolar Synaptic Weights
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Solution Overview
Problem
Current neuromorphic computing technologies cannot effectively represent both positive and negative weights using a single memory device, requiring additional non-volatile memory devices and periphery circuits for differential read operations.
Innovation Solution
A double-gate FinFET with four terminals, utilizing ferroelectric gate dielectric and asymmetric interfacial layers, allows for the representation of both positive and negative weights within a single device, reducing unit cell size and eliminating the need for reference subtraction circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single-gate FET structures are used for neuromorphic computing, then device simplicity is maintained, but the ability to represent both positive and negative weights is lost, requiring additional memory devices and periphery circuits
Solution Approach 1:
The channel region is segmented into two distinct fins: a first fin with a first ferroelectric layer and interfacial layer, and a second fin with a second ferroelectric layer and interfacial layer. Each fin can independently represent different weight polarities, enabling both positive and negative weight representation within a single device structure without requiring additional memory cells.
Solution Approach 2:
The invention transitions from a planar single-gate structure to a three-dimensional double-gate FinFET architecture. By adding the vertical dimension with two stacked fins and their respective gates, the device gains the capability to represent bipolar weights while actually reducing the overall unit cell footprint compared to using multiple separate devices.
2Adaptability or versatility
If additional non-volatile memory devices are used for differential read operations, then both positive and negative weights can be represented, but device complexity and circuit size increase
Solution Approach 1:
The invention merges the functionality of multiple memory devices into a single double-gate FinFET structure. The first and second fins with their respective ferroelectric layers and gates are combined in a stacked configuration, integrating both positive and negative weight representation capabilities into one compact unit cell, thereby eliminating the need for separate reference memory cells and differential read circuits.
Solution Approach 2:
The double-gate FinFET structure serves multiple functions within a single device: the first fin represents positive weights, the second fin represents negative weights, and the shared drain current region enables unified read operations. This multi-functional design eliminates the need for separate reference devices and periphery circuits, reducing overall unit cell area.
3Adaptability or versatility
If conventional FET structures are used, then manufacturing processes are simpler, but the representation of both positive and negative weights in a single device is not achieved
Solution Approach 1:
The invention applies local quality by creating asymmetric structures within the double-gate FinFET: the first fin has a first ferroelectric layer with specific properties, while the second fin has a second ferroelectric layer with potentially different properties. This local differentiation enables independent control of positive and negative weights while using standard ferroelectric material deposition techniques, maintaining compatibility with existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient representation of both positive and negative weights in neuromorphic computing, reducing the complexity and size of unit cells and periphery circuits, and providing a more efficient deep learning application.
Implementation Method 1
A double-gate FinFET with four terminals, utilizing ferroelectric gate dielectric and asymmetric interfacial layers, allows for the representation of both positive and negative weights within a single device
Data Source
AI summary
An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.