Double-Gate FeFET Structure for Wider Memory Window
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Solution Overview
Problem
Integrating ferroelectric materials with semiconductor device materials and structures while maintaining suitable ferroelectric properties and device performance is challenging, particularly in forming ferroelectric field effect transistors (FeFETs) with oxide semiconductors.
Innovation Solution
The development of FeFET devices with a double gate structure, where a first ferroelectric material layer is disposed between a first gate electrode and one side of a channel layer, and a second ferroelectric material layer is disposed between a second gate electrode and the opposite side of the channel layer, allowing for improved polarization, memory window, and on-current through common or separated gate control modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric materials are integrated with semiconductor device materials and structures, then non-volatile memory functionality is achieved, but device performance and ferroelectric properties deteriorate
Solution Approach 1:
The gate structure is divided into two separate gates (first gate electrode and second gate electrode) positioned on opposite sides of the channel layer. This segmentation allows independent optimization of each gate's function and enables better control over the ferroelectric material integration, thereby maintaining device performance while achieving non-volatile memory functionality.
Solution Approach 2:
The patent transitions from a conventional single-gate planar structure to a double-gate vertical structure where gates are positioned on opposite sides of the channel layer. This dimensional change enables enhanced electrostatic control and improved integration of ferroelectric materials without compromising device performance.
2Device complexity
If a single gate structure is used, then device simplicity is maintained, but polarization and memory window are insufficient
Solution Approach 1:
The gate is segmented into two independent gate electrodes that can be controlled separately or together. This segmentation doubles the effective gating control over the channel layer, significantly enhancing polarization and memory window while maintaining reasonable device complexity through symmetric structure design.
Solution Approach 2:
The first and second gates work together in a combined double-gate configuration, merging their electrostatic control effects to achieve enhanced polarization. The gates can operate in common-mode or differential-mode, providing flexibility while achieving superior memory performance.
3Reliability
If ferroelectric material layers are integrated between gate electrodes and channel layers, then memory window and on-current are improved, but integration difficulty increases
Solution Approach 1:
The ferroelectric material is segmented into two separate layers (first ferroelectric material layer and second ferroelectric material layer), each positioned between a gate electrode and the channel layer. This segmentation allows independent optimization of each interface, reducing integration complexity while achieving enhanced memory window and on-current through cumulative effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances remnant polarization, memory window, and on-current in FeFET-based memory devices, providing improved reliability and performance by maintaining ferroelectric properties and enabling non-destructive reading of logic states.
Implementation Method 1
a first ferroelectric material layer disposed between a first gate electrode and a first side of the channel layer, and a second ferroelectric material layer disposed between a second gate electrode and a second side of the channel layer
Data Source
AI summary
A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.


