Double Gate FET Reduces On-Resistance and Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor transistor devices face challenges in achieving high RF performance and low on-resistance while minimizing semiconductor area and cost, with existing solutions limited by complex processes, high parasitic capacitance, and inability to operate as both enhancement and depletion mode devices.
Innovation Solution
A double gate FET structure is introduced, featuring multiple channels and gate regions without a dielectric layer, allowing for improved carrier confinement and transport control, reducing parasitic capacitance, and enabling both enhancement and depletion mode operation without requiring expensive Silicon On Insulator techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is present between gate electrode and channel, then gate insulation is improved, but parasitic capacitance increases and RF performance deteriorates
Solution Approach 1:
The patent removes the dielectric layer between the gate electrode and the channel, extracting the harmful element (parasitic capacitance) while maintaining gate control functionality through the heterostructure interface itself
2Device complexity
If single gate structure is used, then device simplicity is maintained, but control over carrier transport and threshold voltage is insufficient
Solution Approach 1:
The gate control is segmented into two independent gates (first gate and second gate) that can be biased separately, allowing independent control of carrier transport and threshold voltage to achieve both enhancement and depletion mode operation
Solution Approach 2:
The patent adds a vertical dimension to gate control by stacking two gates at different positions relative to the channel, enabling multi-dimensional control of carrier flow and threshold voltage adjustment
3Reliability
If complex SOI processes are used, then device performance is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent replaces expensive Silicon-On-Insulator processes with a simpler heterostructure-based approach using standard semiconductor materials and processes, achieving comparable or superior performance without the need for complex SOI fabrication
4Area of stationary object
If device area is reduced, then integration density is improved, but on-resistance increases and efficiency decreases
Solution Approach 1:
The patent uses composite heterostructure materials (e.g., AlGaAs/GaAs, AlGaN/GaN) with superior electron mobility and saturation velocity to achieve low on-resistance in a compact area, eliminating the trade-off between size and efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double gate configuration significantly reduces on-resistance, enhances RF performance, and provides greater control over threshold voltage, achieving superior RF performance and cost-effectiveness by eliminating the need for complex SOI processes and dielectric layers.
Implementation Method 1
The electrons generated in the thin n-type wide-bandgap layer drop completely into the narrow-bandgap layer where are free to move without being affected by impurity scattering. This method to create an electron channel is called modulation doping.
Implementation Method 2
High electron mobility transistor (HEMT), also known as heterostructure FET (HFET), is a field effect transistor incorporating a junction between two materials with different bandgaps (i.e., a heterojunction) used as channel
Implementation Method 3
A double gate FET structure is introduced, featuring multiple channels and gate regions without a dielectric layer, allowing for improved carrier confinement and transport control
Data Source
AI summary
A novel semiconductor power transistor is presented. The semiconductor structure is simple and is based on a FET structure, where multiple channels and multiple gate regions are formed in order to achieve a lower specific on-resistance, and a higher control on the transport properties of the device. No dielectric layer is present between gate electrodes and device channels, decreasing the parasitic capacitance associated with the gate terminal. The fabrication of the device does not require Silicon On Insulator techniques and it is not limited to Silicon semiconductor materials. It can be fabricated as an enhancement or depletion device with much more control on the threshold voltage of the device, and with superior RF performance.