Double-Gate Fin-FET DRAM Cell Structure
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Solution Overview
Problem
Conventional DRAM devices face challenges with reduced transistor width due to miniaturization, leading to decreased current switching capability, increased leakage currents, and complexity in manufacturing processes, particularly with vertically arranged transistors and floating body effects.
Innovation Solution
A method for fabricating a DRAM cell structure with a double-gate fin-FET, involving the formation of line-shaped trenches, silicon islands, and buried word lines, along with source/drain regions and a gate dielectric layer, to create a fin channel structure with a buried gate electrode, enhancing current driver capability and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the transistor width is reduced to achieve smaller memory cell area, then the memory cell area is reduced, but the current switching capability is decreased
Solution Approach 1:
The patent transitions from planar transistors to vertically arranged double-gate fin-FETs, utilizing the third dimension to maintain transistor width while reducing the lateral footprint. The fin structure extends vertically into the substrate, allowing the channel width to be maintained in the vertical dimension while the lateral cell area is reduced.
Solution Approach 2:
The patent employs a composite structure combining silicon fin channels with multiple gate electrodes (front gate and back gate), creating a double-gate fin-FET. This composite architecture allows independent control of channel conduction through two gates, enhancing current switching capability while maintaining a compact lateral footprint.
2Power
If the gate oxide thickness is reduced to maintain current driver capability with reduced transistor width, then the current driver capability is maintained, but the leakage current is increased
Solution Approach 1:
By moving to a vertical fin-FET structure, the patent maintains an effective channel width in the vertical dimension that is independent of the lateral scaling. This allows the use of thicker gate oxides without compromising current driver capability, as the vertical channel width compensates for the reduced lateral dimensions.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure from planar to vertical fin configuration, fundamentally altering the relationship between gate oxide thickness and current driver capability. The vertical fin structure decouples the effective channel width from the lateral scaling, allowing optimization of gate oxide thickness to reduce leakage while maintaining drive current.
3Power
If vertically arranged transistors are used to utilize the third dimension and obtain larger transistor widths, then the transistor width is increased, but the manufacturing complexity is increased
Solution Approach 1:
The patent segments the gate structure into two separate gates (front gate and back gate) that can be formed at different processing stages. The first gate is formed before the fin structure is fully developed, and the second gate is formed after, allowing independent optimization of each gate's formation process and reducing overall manufacturing complexity.
Solution Approach 2:
The patent performs preliminary formation of the first gate electrode before completing the fin structure and second gate formation. This preliminary action allows the first gate to be established early in the process, simplifying subsequent steps and reducing the complexity of coordinating multiple simultaneous operations.
4Ease of manufacture
If conventional planar transistors are used, then the manufacturing process is simpler, but the current switching capability is reduced due to miniaturization
Solution Approach 1:
The patent maintains manufacturing simplicity by using standard semiconductor fabrication techniques (lithography, etching, deposition, ion implantation) applied to a vertical fin structure rather than requiring entirely new process equipment. The vertical geometry is achieved through modified etching and deposition steps that are extensions of conventional processes.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure from planar to vertical fin configuration, fundamentally altering the relationship between gate oxide thickness and current driver capability. The vertical fin structure decouples the effective channel width from the lateral scaling, allowing optimization of gate oxide thickness to reduce leakage while maintaining drive current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves current switching capability and reduces leakage currents while simplifying the manufacturing process, addressing the limitations of conventional DRAM devices by enabling a more efficient and litho-friendly DRAM cell structure with a double-gate fin-FET.
Implementation Method 1
implanting dopants into the top silicon islands through the recessed implant windows, to thereby form source/drain regions
Data Source
AI summary
A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.