Double-Gate Flash Memory Source-Side Injection
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Solution Overview
Problem
The existing floating gate flash memory devices face issues with low injection efficiency, high power consumption, device punchthrough, and threshold voltage drift due to the high voltage applied to the drain, which limits the ability to shrink the technology node and critical dimension, leading to readout errors and poor programming efficiency.
Innovation Solution
A floating gate type double-gate flash memory device utilizing a source side injection compilation mechanism with a double-gate structure, where polysilicon gates and control gates are arranged in parallel with polysilicon floating gates and insulating layers, allowing for a thin channel electron layer under the gates and a thick layer under the control gates, enabling efficient hot electron injection and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied to the drain to ensure high generation rate of channel hot electrons, then the generation rate of hot electrons is improved, but the device is prone to punchthrough and failure, especially when device size is reduced to 100 nm
Solution Approach 1:
The single gate structure is segmented into a control gate and a floating gate that are spatially separated and independently controllable. This segmentation allows the control gate to be optimized for hot electron generation while the floating gate is optimized for charge storage, resolving the contradiction between high voltage requirements and device reliability.
Solution Approach 2:
The gate structures are arranged in a staggered spatial configuration rather than being coplanar. This dimensional arrangement creates distinct electric field regions: one for efficient hot electron generation near the control gate and another for charge storage at the floating gate, eliminating the punchthrough problem while maintaining high generation rate.
2Productivity
If high voltage is applied to both drain and gate to ensure high generation rate and injection efficiency of channel hot electrons, then the injection efficiency is improved, but the current power consumption increases
Solution Approach 1:
The gate function is segmented into control gate for voltage regulation and floating gate for charge storage. This allows the control gate to maintain optimal voltage for injection efficiency while the floating gate operates at lower voltage during programming, reducing overall power consumption.
Solution Approach 2:
Different voltage levels are applied to different parts of the gate structure locally. The control gate receives higher voltage during programming to ensure injection efficiency, while the floating gate operates at lower voltage, creating localized optimal conditions for each function and reducing total power consumption.
3Quantity of substance
If the critical dimension of flash memory is reduced to sub-100 nm to increase storage density, then the storage density is improved, but the short channel effect causes threshold voltage drift leading to readout errors
Solution Approach 1:
The double-gate structure segments the electrostatic control into two independent gates, effectively doubling the gate-controlled area. This enhanced control compensates for the short channel effects that become prominent at sub-100 nm dimensions, stabilizing threshold voltage while enabling higher storage density.
Solution Approach 2:
The gate control is extended from a single-plane configuration to a staggered three-dimensional arrangement. This dimensional change increases the effective gate control area without proportionally increasing the device footprint, providing stronger electrostatic control at reduced dimensions and preventing threshold voltage drift.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double-gate structure effectively increases storage density, reduces critical dimension, and mitigates short channel effects such as threshold voltage drift, improving programming efficiency and reducing power consumption while enabling technology node upgrades.
Implementation Method 1
enabling efficient hot electron injection and reducing power consumption
Implementation Method 2
utilizing a source side injection compilation mechanism
Implementation Method 3
mitigates short channel effects such as threshold voltage drift
Data Source
AI summary
The present invention discloses a floating gate flash memory device, comprising: a P-type substrate which has a source and a drain, and a first polysilicon gate, a first control gate and a second polysilicon gate and a second control gate which are respectively located in parallel on the upper and lower sides of the substrate, first and second polysilicon floating gates being respectively provided between the first and second control gates and the substrate; the floating gate flash memory device of the present invention utilizes a double-gate structure, can solve the problems such as the poor programming efficiency of the floating gate flash memory and the high programming current power consumption, by using the compilation mechanism of source side injection.