Double Gate IGBT With Optimized Gate Width Ratio
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Solution Overview
Problem
IGBTs with a double gate structure have limited energization capability of their parasitic diodes, particularly at higher voltage ratings, which restricts the ability to reduce or eliminate the need for free-wheeling diodes, leading to increased current path lengths and reduced performance.
Innovation Solution
The semiconductor device incorporates a double gate structure with a trench gate on the front side and a planar gate on the back side, featuring control electrodes with specific stripe shapes and gate width ratios to enhance the energization performance of the parasitic diode, allowing for improved current handling and reduced switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the N base layer is made thicker to increase withstand voltage, then the voltage blocking capability is improved, but the current path becomes longer and the energization performance of the parasitic diode deteriorates
Solution Approach 1:
The patent divides the gate control into two separate gates: a front gate for controlling the main IGBT channel and a back gate for controlling the parasitic diode energization. This segmentation allows independent optimization of voltage blocking (through N base layer thickness) and diode energization (through back gate control), resolving the contradiction between these two requirements.
Solution Approach 2:
The back gate is used to preliminarily energize the parasitic diode before the main current flows through the IGBT. By applying a forward bias to the back gate, excess carriers are injected into the N base layer in advance, ensuring sufficient diode energization even when the N base layer is thick for high voltage applications.
2Loss of energy
If a double gate structure is used to reduce turn-off loss, then the switching performance is improved, but the energization capability of the parasitic diode is not fully utilized
Solution Approach 1:
The back gate structure is designed to serve multiple functions: it controls the parasitic diode energization, assists in turn-off by extracting excess carriers from the N base layer, and can independently modulate the diode current. This multi-functionality resolves the contradiction by making the double gate structure fully utilize the parasitic diode's energization capability while maintaining low turn-off loss.
Solution Approach 2:
The patent dynamically controls the back gate voltage to optimize both turn-off loss and diode energization. During turn-off, the back gate voltage is adjusted to extract excess carriers and reduce switching loss. During normal operation, the back gate voltage is adjusted to provide sufficient diode energization. This dynamic control resolves the contradiction between these two opposing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the energization performance of the parasitic diode by optimizing the gate width ratio, enabling smaller or elimination of free-wheeling diodes, reduced turn-off switching losses, and maintaining low ON voltage characteristics, thus enhancing the overall efficiency and compactness of the IGBT.
Implementation Method 1
a first control electrode respectively switching conductive states and non-conductive states between the first semiconductor layer and the plurality of third semiconductor layers in accordance with electrical signals
Implementation Method 2
a P base layer and the N base layer function as a PN diode
Data Source
AI summary
The plurality of first control electrodes extend in a first direction in a planar view, the plurality of second control electrodes extend in a second direction in a planar view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate which faces the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or higher than 1.0.