Double Gate Ion Sensitive Field Effect Transistor for DNA Sequencing
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Solution Overview
Problem
Current ion-sensitive field effect transistors (ISFETs) have limitations in density and detection limits, making DNA sequencing less cost-effective and requiring larger sample sizes due to the need for separate access transistors, which increases device footprint and reduces sensitivity.
Innovation Solution
The development of double-gate ISFETs with a second gate that acts as an access transistor, allowing for a smaller device footprint and increased density in arrays, and a method to monitor analytes by controlling the voltage of the second gate, enabling detection of smaller sample sizes with lower detection limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a separate access transistor is used in conventional ISFETs, then the device can control current flow, but the device footprint increases and density decreases
Solution Approach 1:
The patent merges the access transistor function directly into the gate structure of the ISFET, creating a double-gate configuration where the first gate serves as the access transistor gate and the second gate serves as the sensing gate. This integration eliminates the need for a separate access transistor, thereby reducing the device footprint while maintaining current control capability.
Solution Approach 2:
The first gate structure in the double-gate ISFET performs multiple functions: it acts as both the access transistor gate for controlling current flow and as part of the capacitive coupling structure for sensing. This multi-functionality reduces the overall device complexity and area requirement.
2Productivity
If device footprint is reduced to increase density, then more ISFETs can be placed per chip, but detection sensitivity may be compromised
Solution Approach 1:
The patent implements a nested structure where the first floating gate is capacitively coupled to the second gate, with the first insulating layer forming a capacitor structure. This nested capacitive coupling allows for efficient signal transduction while maintaining a compact footprint, enabling high density without sacrificing detection sensitivity.
Solution Approach 2:
The double-gate configuration adds a vertical dimension to the device architecture, with gates stacked above each other rather than extending horizontally. This vertical arrangement reduces the lateral footprint of the device while maintaining the necessary sensing and control functions, thereby increasing chip density.
3Device complexity
If conventional single-gate ISFETs are used, then the device structure is simpler, but the detection limit is higher and sensitivity is reduced
Solution Approach 1:
The nested capacitive coupling structure with the first floating gate and second gate enhances the electric field interaction with analytes, improving detection sensitivity. The capacitive coupling amplifies the sensing signal while maintaining a manageable device complexity through systematic design.
Solution Approach 2:
The patent employs a composite gate structure with different insulating materials (first insulating layer and second insulating layer) having different dielectric properties, optimized for their respective functions. This composite structure enhances overall device performance and sensitivity while managing complexity through material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more ISFETs per area, reducing the size of individual devices and enabling detection of smaller analyte concentrations, thereby enhancing the cost-effectiveness and sensitivity of DNA sequencing and other analytical applications.
Implementation Method 1
a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate
Implementation Method 2
a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material
Data Source
AI summary
Devices that include a substrate; a source region and a drain region formed within the substrate and having a channel region provided therebetween; a first insulating layer formed over the channel region; a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material; and a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate.