Double-Gate Non-Volatile Memory Cell Gate Formation
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Solution Overview
Problem
Dual-gate memory cells face challenges in achieving precise control over the relative position of the control transistor gate and the storage transistor gate, leading to poor electrical performance and difficulties in establishing reliable electrical contact due to the small dimensions of the control gate, which increases the risk of short-circuiting.
Innovation Solution
A method involving the formation of a control gate for the memory transistor by depositing a semiconductor layer to cover the relief of the control transistor gate, followed by chemical mechanical polishing to extend the contact surface and facilitate easier connection via alignment with upper wiring layers, thereby improving the accessibility for silicidation and reducing the risk of short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the control gate of the memory transistor is made with small dimensions to increase integration density, then the integration density is improved, but the electrical contact reliability deteriorates and the risk of short-circuiting increases
Solution Approach 1:
The patent extends the control gate structure vertically by forming it as a spacer on the side of the control transistor gate. This three-dimensional approach increases the contact surface area available for electrical connection without increasing the planar footprint, thereby maintaining high integration density while improving contact reliability and reducing short-circuit risks.
Solution Approach 2:
The control gate of the memory transistor serves as an intermediary structure that is formed as a spacer on the control transistor gate. This spacer structure provides an extended surface that facilitates reliable electrical contact between the control gate and the source/drain regions, mediating the connection between the two transistors in the dual-gate configuration.
2Device complexity
If the relative position of the control transistor gate and storage transistor gate is not precisely controlled, then the manufacturing complexity is reduced, but the electrical performance deteriorates
Solution Approach 1:
The control gate of the memory transistor is formed as a spacer that is self-aligned to the control transistor gate. This self-aligned formation process automatically establishes the correct relative position between the two gates without requiring additional photolithography steps or complex alignment procedures, thereby reducing manufacturing complexity while ensuring precise positioning for optimal electrical performance.
Solution Approach 2:
The spacer structure is formed preliminarily during the gate formation process itself, before subsequent processing steps. This preliminary formation of the control gate as a spacer establishes the correct geometric relationship between the control transistor and memory transistor gates, ensuring proper electrical performance is achieved without requiring later adjustment or additional alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the contact surface area of the control gate, simplifies the positioning of connection vias, and improves electrical connection reliability, reducing the risk of short-circuits and allowing for more precise alignment without the need for additional photolithography steps.
Implementation Method 1
formation of the control gate of the memory transistor, preferably comprising a step of depositing a layer of a material, preferably a semiconductor
Implementation Method 2
CMP chemical mechanical polishing carried out so as to remove, above the relief of the gate of the control transistor, said other layer and part of the layer in a semiconductor material
Data Source
Figure 1a~1b
Figure 2a~2c
Figure 2d~2f
AI summary
The invention relates to a method for manufacturing a double-gate non-volatile memory cell (100), in which the following steps are carried out: o at least partial formation of a gate (130) of the control transistor, including in particular obtaining a relief (132) on a substrate (160, 162); o formation of a control gate (140) of the storage transistor, including a step of depositing a layer (210) of a semiconductor material so as to cover at least the relief (132) of the gate (130) of the control transistor; characterized in that the formation of the control gate (140) of the storage transistor further comprises the following steps of: deposition on the layer (210) of a semiconductor material of another layer (220); chemical mechano-polishing (CMP) carried out so as to remove, above the relief (132) of the grid (130) of the control transistor, said other layer (220) and part of the layer (210) in a semiconducting material;removal of said other remaining layer (220) on either side of the relief (132) of the gate (130) of the control transistor; etching of the layer (210) in a semiconducting material so as to remove this material above the relief (132) of the gate (130) of the control transistor and to leave only a pattern (142) on at least one side of the relief (132) of the gate (130) of the control transistor.;