Double-Gate MFMIS-FET Structure for Higher ON Current
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Solution Overview
Problem
Ferroelectric memory devices, such as FeFET and FeRAM, face limitations due to low ON current, which affects their performance in high-speed data applications by causing slow read and write speeds.
Innovation Solution
The implementation of a double gate metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) structure, which includes a lower and upper gate electrode to control the polarization state of ferroelectric structures, resulting in a higher ON current and improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single gate ferroelectric FET structure is used, then the device structure is simple, but the ON current is low resulting in slow read and write speeds
Solution Approach 1:
The gate structure is segmented into two separate gates (first gate electrode and second gate electrode) positioned on opposite sides of the channel. This segmentation allows independent control of the channel from both sides, enabling enhanced carrier injection and higher ON current compared to a single gate structure, thereby improving read and write speeds.
Solution Approach 2:
The invention transitions from a single-plane gate control to a three-dimensional dual-gate configuration where gates are positioned on opposite sides of the channel. This dimensional change enables simultaneous control of the channel from both top and bottom, creating a more effective electric field distribution and improving carrier transport efficiency.
2Power
If a double gate MFMIS-FET structure is implemented, then the ON current is enhanced, but the device structure becomes more complex
Solution Approach 1:
The invention combines two gate structures into a single integrated device, where both gates work synergistically to control the channel. The first and second gate electrodes are merged into one functional unit that provides coordinated control, enabling enhanced ON current through combined electric field effects while maintaining a unified device architecture.
Solution Approach 2:
The dual gate structure provides multi-functional control capabilities, where each gate can independently or jointly control the channel conductivity. This multi-functionality allows the device to achieve higher ON current states while maintaining the ability to operate in different modes, effectively utilizing the additional structural complexity for enhanced performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double gate MFMIS-FET structure enhances the ON current, thereby improving the performance of ferroelectric memory devices by increasing their speed and expanding their applicability to high-speed data applications.
Implementation Method 1
Some promising candidates for next generation memory technology utilize ferroelectricity to store data, such as ferroelectric field-effect transistor (FeFET) memory
Implementation Method 2
a lower and upper gate electrode to control the polarization state of ferroelectric structures
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.