Double-Gate Carbon Nanotube Transistor for Short-Channel Control

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Solution Overview

Problem

The semiconductor industry faces challenges in transistor scaling due to unwanted short channel effects such as drain-induced barrier lowering and large subthreshold swing, which are exacerbated by the reduction in transistor size, and traditional 3D bulk crystal channel materials suffer from carrier scattering and threshold voltage variations.

Innovation Solution

A double-gate carbon nanotube transistor is developed, where carbon nanotubes are formed over a dielectric layer, a dummy gate is removed, and a gate dielectric is formed to encircle the nanotubes, reducing short-channel effects by suspending the nanotubes and creating a double-gate structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistor size is reduced to increase density, then productivity is improved, but short channel effects worsen

Engineering Contradiction:
Improvetransistor densityVSAvoidshort channel effects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar 2D gating to 3D wrap-around gating, where the gate electrode surrounds the carbon nanotube channel in multiple dimensions. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects while maintaining scaled dimensions for high density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs carbon nanotubes as the channel material, utilizing their unique one-dimensional crystal structure with superior carrier mobility and electrostatic control compared to traditional bulk semiconductor materials. This composite approach combines the advantages of nanoscale confinement with high-quality material properties.

Inventive Principle:
Principle #40Composite materials

2Reliability

If channel body thickness is reduced to mitigate short channel effects, then reliability is improved, but manufacturing precision worsens

Engineering Contradiction:
Improveshort channel effectsVSAvoidbody thickness control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the fundamental parameter of channel geometry from bulk 3D structure to one-dimensional nanotube structure. This parameter change eliminates the need for precise thickness control while maintaining excellent electrostatic control and suppressing short channel effects through the inherent properties of carbon nanotubes.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If 3D bulk crystal channel materials are used, then ease of manufacture is improved, but reliability worsens due to carrier scattering

Engineering Contradiction:
Improvematerial processingVSAvoidcarrier scattering
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent uses carbon nanotubes with their unique one-dimensional crystal structure that inherently provides superior carrier mobility by eliminating bulk scattering mechanisms. The nanotube structure maintains crystalline quality while providing superior electrical transport properties compared to bulk materials.

Inventive Principle:
Principle #40Composite materials

4Reliability

If body thickness is reduced to improve short channel control, then reliability is improved, but device complexity worsens due to threshold voltage variations

Engineering Contradiction:
Improveshort channel controlVSAvoidthreshold voltage control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the channel from bulk structure to one-dimensional nanotubes, which provides natural immunity to threshold voltage variations. The quantized energy levels and superior electrostatic control in nanotubes eliminate the sensitivity to dimensional variations that plagues bulk-based devices.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11930696B2Fabrication method of a double-gate carbon nanotube transistor
Publication Date: 2024.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11930696B2 patent drawing
  • US11930696B2 patent drawing
  • US11930696B2 patent drawing

AI summary

A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.