Double Gate Neuromorphic Memory Device

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Solution Overview

Problem

Existing neuromorphic memory devices face challenges in improving update characteristics and maintaining non-linear voltage dependence, which affects the accuracy and efficiency of deep neural network training calculations.

Innovation Solution

A double gate neuromorphic memory device is proposed, featuring a top gate and a bottom gate with a stacked structure of electrolyte, ion reservoir, and gate electrode layers. This design maximizes the interface for switching and improves device characteristics by integrating both sputter and ALD processes compatible with CMOS technology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single gate structure is used in neuromorphic memory devices, then the device structure is simpler, but the update characteristics and switching performance are insufficient

Engineering Contradiction:
Improveupdate characteristicsVSAvoidgate structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate structure is segmented into two separate gates (top gate and bottom gate) that independently control the channel area. This segmentation allows each gate to contribute to switching performance without requiring the other to be overly complex, resolving the contradiction between improved update characteristics and device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-plane gate control to a three-dimensional double gate structure where gates are positioned on opposite sides of the channel area. This dimensional change enables enhanced control over ion movement and switching characteristics without proportionally increasing overall device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the top gate is positioned close to source and drain electrodes, then the switching interface is maximized, but the channel area exposure is reduced affecting control flexibility

Engineering Contradiction:
Improveswitching characteristicsVSAvoidcontrol flexibility
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The top gate is positioned to partially overlap the channel area and partially overlap the source/drain electrodes, creating different local control zones. The portion over the channel provides strong switching control, while the exposed channel sections maintain operational flexibility, resolving the contradiction between maximizing switching interface and preserving control flexibility.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The double gate neuromorphic memory device enhances switching characteristics and reduces power consumption, enabling efficient intelligent training calculations comparable to or exceeding existing digital systems.

Implementation Method 1

A neuromorphic memory device may include an ion movement-based double gate structure that causes movement of ions between the gate electrode layer and the channel area by applying an external voltage Vg to the top gate

Methodology Applied
Scientific EffectIon movement: Ion Repulsion/Attraction

Implementation Method 2

integrating both sputter and ALD processes compatible with CMOS technology

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS20250077855A1Double gate neuromorphic memory device and manufacturing method thereof
Publication Date: 2025.03.06 POSTECH ACADEMY INDUSTRY FOUNDATION
  • US20250077855A1 patent drawing
  • US20250077855A1 patent drawing
  • US20250077855A1 patent drawing

AI summary

The present disclosure relates to a double gate neuromorphic memory device and a manufacturing method thereof. The double gate neuromorphic memory device is an electrochemical device, and includes a bottom gate provided on an upper portion of a semiconductor substrate, a channel area surrounding the upper portion and side surfaces of the bottom gate, a source electrode and a drain electrode provided in contact with both sides of the channel area, and a top gate provided on an upper portion of a channel area between the source electrode and the drain electrode.