Double Gate Non-Volatile Memory Device Data Retention
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Solution Overview
Problem
The existing finFET non-volatile memory devices face data retention issues due to the same control gate being used for both programming and sensing, which causes stored charge to leak away during the sensing process.
Innovation Solution
A double gate non-volatile memory device is designed with an access gate adjacent to one sidewall portion and a control gate on the other, separated by an intermediate gate oxide layer, allowing for separation of sensing and programming functionalities, thereby reducing exposure to biasing voltage during sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same control gate is used for both programming and sensing, then the device structure is simple, but data retention is adversely affected due to charge leakage during sensing
Solution Approach 1:
The single control gate is segmented into two separate gates: a first control gate for programming and a second control gate for sensing. This segmentation allows independent optimization of each gate's function, preventing charge leakage during sensing while maintaining the ability to program the device.
Solution Approach 2:
The sensing function is extracted from the programming control gate. The second control gate is specifically designed and positioned to enable sensing operations without affecting the charge stored in the charge trapping layer, thereby separating the harmful sensing action from the charge storage region.
2Ease of operation
If biasing voltage is applied during sensing, then sensing operation is enabled, but stored charge leaks away from the charge trapping layer
Solution Approach 1:
The second control gate acts as an intermediary for sensing operations. It enables the application of biasing voltage necessary for sensing while being positioned and configured to minimize direct interaction with the charge trapping layer, thus preventing charge leakage during the sensing process.
Solution Approach 2:
The second control gate is positioned adjacent to a specific sidewall portion of the channel region, creating localized electric field control. This local quality approach allows sensing to be performed in a specific region without subjecting the entire charge trapping layer to harmful biasing conditions.
Data Source
AI summary
The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.