Double-Gate Compensation Transistor Layout for OLED Flicker Control

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Solution Overview

Problem

Organic light emitting diode displays face flickering issues during low-frequency display due to leakage in compensation transistors, which are affected by surrounding signals.

Innovation Solution

A display substrate design with a double-gate transistor structure for compensation transistors, where the first compensation gate pattern partially or completely overlaps the compensation channel portion, and a shielding pattern is used to stabilize voltage and shield the transistors from external signals, along with a top-and-bottom gate structure for reset transistors to prevent leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-gate transistor structure is used for compensation transistors, then the device complexity is reduced, but the transistor leakage increases causing flickering during low-frequency display

Engineering Contradiction:
Improvetransistor structure complexityVSAvoidtransistor leakage
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The compensation transistor is divided into two gates: a first compensation gate pattern (bottom gate) and a second compensation gate pattern (top gate). This segmentation allows independent control of the channel from both sides, effectively reducing leakage current while maintaining manageable device complexity through modular gate structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension by stacking the first compensation gate pattern below the compensation active layer and the second compensation gate pattern above it. This three-dimensional double-gate configuration provides enhanced control over the compensation channel, reducing leakage without significantly increasing planar device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If no shielding pattern is used, then the device complexity is reduced, but the compensation transistor is affected by surrounding signals causing leakage

Engineering Contradiction:
Improveshielding structure complexityVSAvoidsignal interference
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

A shielding pattern is introduced as an intermediary element between the compensation transistor and surrounding signal sources. This shielding structure acts as a barrier that blocks or filters interfering signals from adjacent circuits, protecting the compensation transistor from noise while maintaining reasonable device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If the first compensation gate pattern does not overlap the compensation channel portion, then the manufacturing precision is reduced, but the shielding effect is insufficient

Engineering Contradiction:
Improvegate pattern alignment precisionVSAvoidsignal interference
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The first compensation gate pattern is positioned in the vertical dimension below the compensation active layer, creating an overlapping configuration when viewed in plan. This vertical stacking provides effective shielding of the compensation channel from lateral signal interference while reducing the lateral alignment precision requirements compared to planar overlapping structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12563923B2Display substrate that includes an initialization signal film layer with a plurality of portions and sub-portions, method of manufacturing the same and display device
Publication Date: 2026.02.24 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12563923B2 patent drawing
  • US12563923B2 patent drawing
  • US12563923B2 patent drawing

AI summary

A display substrate includes: a base substrate, a plurality of sub-pixels arranged on the base substrate, a plurality of gate lines, and a plurality of first compensation gate patterns; the sub-pixel includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a compensation transistor; the compensation transistor includes a second compensation gate pattern, the first compensation gate pattern is located between a corresponding second compensation gate pattern and the base substrate, the first compensation gate pattern is coupled to a DC signal output terminal, and the second compensation gate pattern is coupled to a corresponding gate line; the compensation transistor includes a compensation active layer, the compensation active layer is located between the first compensation gate pattern and the second compensation gate pattern, and the compensation active layer includes a compensation channel portion.