Double Gate Semiconductor Device for RF Capacitance Reduction
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Solution Overview
Problem
In RF devices on silicon-on-insulator substrates, the off-capacitance (Coff) and parasitic capacitance between the source/drain (Cds) are not low enough, particularly with the advent of 5G cellular mobile communication, necessitating a reduction in these parameters to improve device performance.
Innovation Solution
A semiconductor device with a double gate structure is implemented, featuring a buried dielectric layer, first and second gate structures, source/drain regions, front-side and backside metallization, and conductive contacts. The double gate structure, along with strategically positioned source/drain regions and metallization, effectively reduces off-capacitance and parasitic capacitance by allowing for better control of the carrier channel region, thereby minimizing signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single gate structure is used on SOI substrate, then the device can be fabricated using standard IC technology, but the off-capacitance and parasitic capacitance are not low enough for 5G applications
Solution Approach 1:
The gate structure is segmented into two separate gates: a front gate formed on the front surface of the SOI substrate and a back gate formed on the back surface of the SOI substrate. This segmentation allows independent control of the channel from both surfaces, enabling better capacitance control while maintaining compatibility with standard fabrication processes
Solution Approach 2:
The invention transitions from a single-plane gate control to a three-dimensional dual-plane gate control by placing gates on both the front and back surfaces of the SOI substrate. This dimensional expansion enables enhanced electric field control throughout the entire substrate thickness, effectively reducing off-capacitance and parasitic capacitance
2Reliability
If the thickness of the semiconductor layer is reduced to lower capacitance, then off-capacitance decreases, but the control over the channel becomes insufficient
Solution Approach 1:
By dividing the gate control into front and back segments, the invention maintains effective channel control even with thinner semiconductor layers. Each gate independently influences the channel, providing redundant control mechanisms that compensate for the reduced layer thickness
Solution Approach 2:
The invention changes the control parameters by introducing dual-gate voltage control, allowing independent adjustment of front gate voltage (Vfg) and back gate voltage (Vbg). This enables precise tuning of the channel characteristics and capacitance values without requiring changes to the semiconductor layer thickness
Data Source
AI summary
A semiconductor device comprises a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a front-side metallization, a backside metallization, and conductive contacts. The first gate structure and the second gate structure disposed respectively in the front-side and back side of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structures. The front-side metallization is disposed on the front-side of the buried dielectric layer, and the backside metallization is disposed on the backside of the buried dielectric layer. The conductive contacts penetrate the buried dielectric layer and electrically couple the front-side metallization to the backside metallization.