Double-Gate Semiconductor Synapse for Low-Power Weight Setting
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Solution Overview
Problem
Existing NOR flash memory technologies face challenges in independently setting synapse weights for each cell due to limitations in the Fowler-Nordheim tunneling process, leading to high power consumption and difficulty in using polycrystalline semiconductor materials.
Innovation Solution
A semiconductor device with a double-gate structure is designed to perform program and erase operations through Fowler-Nordheim tunneling, allowing independent setting of synapse weights, reducing power consumption, and enabling the use of polycrystalline materials for high integration and ease of array expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the channel hot electron (CHI) process is used for program operation in NOR flash memory, then the device can be manufactured using polysilicon, but high power consumption occurs and single-crystalline silicon must be used instead
Solution Approach 1:
The patent changes the fundamental operating parameter from channel hot electron injection to Fowler-Nordheim tunneling. This parameter change enables the use of polysilicon materials while reducing power consumption, as FN tunneling occurs at lower voltages and currents compared to CHI process
Solution Approach 2:
The patent replaces the thermal/mechanical hot electron injection mechanism with a quantum mechanical tunneling mechanism. This substitution allows program operation to occur at lower power levels while maintaining manufacturability with polysilicon materials
2Use of energy by moving object
If the Fowler-Nordheim tunneling process is applied to NOR flash memory, then power consumption is reduced, but independent program operation for each cell cannot be performed
Solution Approach 1:
The patent segments the gate control by introducing separate control gates for each cell or cell group. This segmentation enables independent program operation for each cell while maintaining the low power consumption benefits of FN tunneling, as each cell can be individually addressed through its dedicated control gate
Solution Approach 2:
The patent applies local quality control by providing individual control mechanisms for each cell or cell group. This allows selective program operation on specific cells without affecting others, enabling independent weight setting while preserving the energy efficiency of the FN tunneling process
3Productivity
If the common source line is used in NOR flash memory array structure, then parallel connection of cells is achieved, but program inhibit cannot be performed in cells sharing the word line
Solution Approach 1:
The patent segments the source region by introducing separate source lines for different cell groups or individuals. This segmentation enables program inhibit functionality for specific cells while maintaining the parallel architecture benefits, as cells can be independently controlled through their dedicated source lines
Solution Approach 2:
The patent adds a new dimension to the array structure by introducing additional control lines (control gate lines and control source lines) that extend the control capability. This dimensional expansion enables program inhibit functionality without compromising the parallel connection efficiency of the base array structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low power consumption and high integration of synapse arrays, improving performance compared to existing NOR flash memory-based neural networks, while facilitating the use of polycrystalline materials for semiconductor devices.
Implementation Method 1
performs program (PGM)/erase (ERS) operation through Fowler-Nordheim (FN) tunneling between double gates
Data Source
AI summary
Embodiments relate to a semiconductor device including a body made of a first conducting semiconductor material, a source and a drain made of a second conducting semiconductor material and formed on the body, a first gate formed on the body with a gate insulating layer interposed between the first gate and the body, a second gate formed opposite the first gate with respect to the body, and an insulating layer stack having a charge storage layer formed between the body and the second gate, and a method for controlling a synapse weight of a target semiconductor device within a neural network including semiconductor devices.