Double-Gate Vertical TFT Backplane for Low-Leakage Mini LED Driving
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Solution Overview
Problem
Existing thin film transistors (TFTs) used in active matrix miniature LED displays face challenges in meeting the high driving capability requirements due to limitations in mobility, stability, and manufacturing complexity, leading to excessive costs and difficulties in large-size applications, as well as issues with TFT leakage current causing uneven brightness.
Innovation Solution
A double-gate vertical channel thin film transistor structure is introduced, featuring a semiconductor layer with a nanoscale thickness, which enables ultra-high on-state current and greater driving capability. The double-gate structure reduces leakage current and allows for control of the threshold voltage, improving the driving capability of LED backplanes and brightness uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon thin film transistors are used, then manufacturing is simpler, but mobility is limited resulting in insufficient driving capability
Solution Approach 1:
The patent employs a composite semiconductor layer structure combining IGZO (indium gallium zinc oxide) and silicon materials. The IGZO layer provides high mobility for superior driving capability, while the silicon layer contributes to manufacturing compatibility. This composite approach resolves the contradiction by achieving both high performance and manufacturability through material composition rather than structural complexity.
2Reliability
If IGZO is used, then mobility is improved, but stability is limited resulting in insufficient reliability
Solution Approach 1:
The dual-layer semiconductor structure combines IGZO and silicon, where the IGZO layer delivers high electron mobility while the silicon layer provides structural stability and reduces defects. The interface between the two materials creates a synergistic effect that enhances overall device reliability while maintaining high mobility performance.
Solution Approach 2:
The patent applies different material properties to different regions of the semiconductor layer. The IGZO layer is positioned to exploit its high mobility characteristics in the active channel region, while the silicon layer provides stable structural support and defect reduction. This local optimization of material placement resolves the stability-mobility contradiction.
3Reliability
If LTPS is used, then mobility is improved, but manufacturing process complexity increases resulting in higher costs
Solution Approach 1:
Instead of using complex LTPS processing, the patent employs a composite structure of IGZO and amorphous silicon that can be manufactured using simpler, more compatible processes. The IGZO layer provides the necessary high mobility without requiring the complex crystallization steps needed for LTPS, thus reducing manufacturing complexity while maintaining performance.
4Ease of manufacture
If conventional TFT structure is used, then manufacturing is simpler, but leakage current is excessive causing uneven brightness
Solution Approach 1:
The composite IGZO-silicon semiconductor layer inherently reduces leakage current through the formation of a depletion region at the material interface and the high-quality crystalline structure of IGZO. This approach maintains manufacturing simplicity while effectively suppressing leakage current that causes brightness non-uniformity in conventional TFTs.
Solution Approach 2:
The patent modifies the semiconductor material parameters by introducing IGZO with its distinct electronic properties. The high electron mobility and appropriate band structure of IGZO change the electrical parameters of the TFT, resulting in reduced off-state leakage current while maintaining ease of manufacture through existing deposition techniques.
Data Source
AI summary
The application discloses a thin film transistor and a light-emitting diode (LED) backplane. The thin film transistor includes: a first gate, a first insulating layer, a first source, a semiconductor layer, a first drain, a second insulating layer, and a second gate; the first insulating layer covers the first gate; the first source, the semiconductor layer, and the first drain are all disposed at a side of the first insulating layer away from the first gate; the second insulating layer covers the first drain, the semiconductor layer, and the first source; and the second gate is disposed on a surface of a side of the second insulating layer away from the first gate, wherein the first source, the semiconductor layer, and the first drain jointly constitute a vertical channel structure.