Double Gate Thin Film Transistor for Display Substrates
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Solution Overview
Problem
Existing thin film transistor array substrates for organic light-emitting display apparatuses face challenges in reducing parasitic capacitance and increasing current driving capability, leading to issues with voltage drop, signal delay, and decreased opening ratio, especially in large-size high-resolution displays.
Innovation Solution
A thin film transistor array substrate with a bottom gate electrode doped with ion impurities and an oxide semiconductor region between the source and drain contact regions, along with a top gate electrode, is used to minimize parasitic capacitance and enhance current driving capability, featuring a double gate structure and reduced channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thin film transistor structure is used, then device complexity is reduced, but parasitic capacitance increases and current driving capability decreases
Solution Approach 1:
The transistor is divided into two separate gate electrodes (bottom gate electrode and top gate electrode) that can be independently controlled. This segmentation allows independent optimization of each gate's function, enabling reduced parasitic capacitance while maintaining current driving capability through coordinated operation of both gates
Solution Approach 2:
The invention transitions from a conventional single-plane gate structure to a three-dimensional stacked gate structure with bottom and top gates positioned at different vertical levels. This dimensional change enables reduced parasitic capacitance by separating the gate electrodes spatially while maintaining effective channel control
2Area of stationary object
If channel length is reduced to increase opening ratio, then opening ratio improves, but signal delay increases due to voltage drop
Solution Approach 1:
The channel region is segmented into two independently controllable sections by the bottom and top gates. This allows the physical channel length to be shortened for increased opening ratio while maintaining effective electrical control through dual-gate operation, reducing signal delay despite reduced length
Solution Approach 2:
The dual-gate structure enables dynamic control of the channel characteristics by independently adjusting the voltage applied to each gate. This dynamic control compensates for the effects of reduced channel length, maintaining signal integrity and reducing delay while preserving high opening ratio
3Reliability
If bottom gate electrode is doped with ion impurities, then conductivity increases, but parasitic capacitance in gate area increases
Solution Approach 1:
Ion impurity doping is applied locally and selectively to specific regions of the bottom gate electrode (source region and drain region) rather than uniformly across the entire gate. This local quality enhancement increases conductivity where needed for current driving while minimizing parasitic capacitance in the gate area by avoiding unnecessary doping in regions where it would contribute to capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance, increases on-current, and enables high-speed operation of large-size high-resolution displays with improved opening ratio and extended lifespan, while maintaining low power consumption.
Implementation Method 1
a bottom gate electrode including a gate area doped with ion impurities and undoped areas on left and right sides of the gate area
Implementation Method 2
an active layer on the bottom gate electrode with a first insulating layer therebetween and including a source contact region, a drain contact region, and an oxide semiconductor region
Implementation Method 3
a top gate electrode on the active layer with a second insulating layer therebetween
Data Source
AI summary
A thin film transistor array substrate includes: a substrate; a bottom gate electrode including a gate area doped with ion impurities and undoped areas on left and right sides of the gate area; an active layer on the bottom gate electrode with a first insulating layer therebetween and including a source contact region, a drain contact region, and an oxide semiconductor region; a top gate electrode on the active layer with a second insulating layer therebetween; and a source electrode in contact with the source contact region and a drain electrode in contact with the drain contact region, the source electrode and the drain electrode being on the top gate electrode with a third insulating layer therebetween. The oxide semiconductor region is between the source contact region and the drain contact region.