Double-Gate TFT Gate Line Layout to Suppress Etching Residue
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The use of double-gate structure oxide semiconductor TFTs in high-resolution liquid crystal displays leads to increased slope differences between gate electrodes, causing etching residues of the source metal and potential leakage between lines, which is exacerbated by misalignment and line width variations.
Innovation Solution
The active matrix substrate design features an upper gate line width greater than the lower gate line width, with both gate electrodes electrically coupled and supplied with equal potential, and includes a configuration with flattening layers to suppress etching residues and improve aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a double-gate structure oxide semiconductor TFT is used to reduce TFT size while maintaining ON current, then the aperture ratio is improved, but etching residues of source metal occur on the side surface due to increased slope (level difference) between gate electrodes
Solution Approach 1:
The patent applies asymmetry by making the upper gate line wider than the lower gate line. This asymmetric design compensates for the slope issue in the double-gate structure, preventing etching residues from occurring on the side surface while maintaining the compact TFT size and high aperture ratio required for ultra-high resolution displays.
2Area of moving object
If the TFT size is reduced to improve aperture ratio in ultra-high resolution displays, then the aperture ratio increases, but the slope between gate electrodes increases causing etching residues
Solution Approach 1:
The asymmetric gate line width design (upper gate line wider than lower gate line) directly addresses the slope issue by creating a compensating geometric configuration that reduces the effective level difference, thereby preventing etching residues while maintaining the reduced TFT size for high aperture ratio.
3Productivity
If oxide semiconductor TFT is used instead of amorphous silicon to achieve higher mobility and smaller size, then the TFT size can be reduced, but etching residues occur due to the double-gate structure's slope
Solution Approach 1:
The asymmetric gate line configuration resolves the manufacturing precision issue inherent in oxide semiconductor TFTs with double-gate structure. By making the upper gate line wider, the design compensates for the slope-induced etching residue problem, enabling the use of high-mobility oxide semiconductors without sacrificing manufacturing quality.
Data Source
AI summary
An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.