Double Gate Thin Film Transistor for OLED Leakage Reduction
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Solution Overview
Problem
Existing OLED displays face challenges in maximizing charge mobility and minimizing leakage current in thin film transistors (TFTs), which are crucial for efficient display performance.
Innovation Solution
A double gate type TFT design is implemented, where the second horizontal and vertical gate electrodes surround the channel region, creating a larger current path when the gate signal is applied and blocking current paths in the off state to reduce leakage, thereby enhancing charge mobility and minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single gate TFT structure is used, then the device complexity is low, but charge mobility is insufficient and leakage current is high
Solution Approach 1:
The gate electrode is segmented into two separate gate electrodes (first gate electrode and second gate electrode) positioned at opposite sides of the semiconductor layer. This segmentation allows independent control of charge carriers from both sides, improving charge mobility and reducing leakage current by utilizing the entire thickness of the semiconductor layer for current conduction.
Solution Approach 2:
The invention transitions from a single-plane gate structure to a three-dimensional configuration where gate electrodes are positioned on both upper and lower surfaces of the semiconductor layer. This dimensional change enables control of charge carriers throughout the volume of the semiconductor, maximizing the current path and improving overall device performance.
2Reliability
If a conventional single gate TFT structure is used, then the manufacturing process is simple, but leakage current cannot be minimized
Solution Approach 1:
The gate electrode is segmented into two separate gate electrodes (first gate electrode and second gate electrode) positioned at opposite sides of the semiconductor layer. This segmentation allows independent control of charge carriers from both sides, improving charge mobility and reducing leakage current by utilizing the entire thickness of the semiconductor layer for current conduction.
Solution Approach 2:
The invention transitions from a single-plane gate structure to a three-dimensional configuration where gate electrodes are positioned on both upper and lower surfaces of the semiconductor layer. This dimensional change enables control of charge carriers throughout the volume of the semiconductor, maximizing the current path and improving overall device performance.
Data Source
AI summary
A TFT, OLED display including the same, and manufacturing method thereof are disclosed. In one aspect, the TFT includes a first gate electrode formed over a substrate and a first insulating layer formed over the substrate and the first gate electrode. A semiconductor layer is formed over the first insulating layer, the semiconductor layer at least partially overlapping the first gate electrode. A second insulating layer is formed over the first insulating layer and the semiconductor layer, the first and second insulating layers having a pair of connection holes formed therethrough. A second gate electrode is electrically connected to the first gate electrode via the connection holes, the connection holes respectively exposing portions of the first gate electrode. Source and drain electrodes are formed over a third insulating layer and electrically connected to the semiconductor layer via the contact holes, the contact holes respectively exposing portions of the semiconductor layer.