Double-Gate TFT Pixel Electrode Layout for High Aperture Ratio
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Solution Overview
Problem
In liquid crystal display devices, the reduction of pixel size to increase resolution is hindered by the large area ratio of gate lines, signal lines, and contact holes to pixel area, which affects the aperture ratio and overall display quality.
Innovation Solution
The design incorporates a double-gate thin-film transistor structure with a specific arrangement of gate lines, signal lines, semiconductor layers, and contact holes, allowing for a reduced number of contact holes in the first direction, enabling smaller pixel sizes and higher resolution while maintaining a higher aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel size is reduced to increase resolution, then the resolution is improved, but the area ratio of gate lines, signal lines, and contact holes to pixel area increases, reducing the aperture ratio
Solution Approach 1:
The patent merges the gate line structure with the transistor configuration by making the gate line extend through the transistor region and serve as a common electrode. This integration reduces the number of separate conductive structures needed, thereby reducing the total area occupied by lines and contact holes while maintaining electrical connectivity, thus improving aperture ratio without sacrificing resolution
Solution Approach 2:
The gate line serves multiple functions: it acts as a scanning signal line for addressing pixels, as a common electrode for the liquid crystal modulation, and as a structural element that defines the transistor gate. This multi-functionality eliminates the need for separate common electrode structures, reducing area consumption and improving aperture ratio while maintaining high resolution
2Area of stationary object
If the number of contact holes is reduced, then the aperture ratio is improved, but the electrical connectivity and signal transmission may be affected
Solution Approach 1:
The patent merges the gate line continuity function with the electrical connectivity function. The gate line extends continuously through the transistor region without interruption, providing both the scanning signal path and the common electrode connection, thereby maintaining electrical connectivity while reducing the number of discrete contact holes needed
Solution Approach 2:
The patent transitions from a planar arrangement with multiple contact holes to a three-dimensional layered structure where the gate line passes through the transistor region in the vertical dimension. This allows electrical connectivity to be maintained through the continuous gate line structure rather than through multiple contact holes in the same plane, improving aperture ratio while preserving connectivity
Data Source
AI summary
According to one embodiment, a liquid crystal display device includes a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a gate line extending in a first direction, a first signal line, a second signal line, a first semiconductor layer, a second semiconductor layer, an insulating film, a first contact hole, a second contact hole, a first pixel electrode and a second pixel electrode. The second contact hole is located opposite to the first contact hole in a second direction intersecting the first direction.