Double-Gate Thin Film Transistors for Better Subthreshold Control
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Solution Overview
Problem
Conventional thin film transistors face challenges in scaling down to smaller dimensions due to limitations in subthreshold swing and variability in fabrication processes, making it difficult to extend their performance into the 10 nm or sub-10 nm range, necessitating new methodologies or technologies for future technology nodes.
Innovation Solution
The introduction of double gate thin film transistors with a second gate on top of the channel material layer to improve electrostatic gate control and ON/OFF ratio, implemented through non-planar architectures that increase effective gate width and drive strength, enabling better performance and integration in advanced semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-gate transistor structures are used, then fabrication processes are simpler and manufacturing is easier, but gate control is insufficient and subthreshold swing cannot be improved below the theoretical limit
Solution Approach 1:
The transistor gate is segmented into two separate gates (first gate and second gate) positioned at opposite sides of the channel material layer. This segmentation allows independent control of the channel from both sides, improving electrostatic control and subthreshold swing performance while maintaining a modular structure that can be integrated into existing fabrication processes
Solution Approach 2:
The patent transitions from a conventional single-plane gate structure to a three-dimensional double-gate configuration where gates are positioned on opposite sides of a thin channel material layer. This dimensional change enables control of the channel from both top and bottom surfaces, significantly improving gate control effectiveness without requiring a complete process overhaul
2Productivity
If transistor dimensions are scaled down to increase density, then more devices fit on chip, but fabrication variability increases and process constraints become overwhelming
Solution Approach 1:
The patent changes the structural parameters of the transistor by introducing a thin channel material layer (5-30 nm thick) with double gates positioned on opposite sides. This parameter change improves the effective gate control area and electrostatic control without requiring proportional scaling of all other dimensions, thereby maintaining manufacturing precision while enabling higher device density
Solution Approach 2:
The patent employs a composite structure consisting of the channel material layer sandwiched between two gate stacks, each comprising gate electrode and gate dielectric. This composite architecture provides enhanced control over the channel while distributing the fabrication requirements across multiple layers that can be processed using existing semiconductor manufacturing techniques
3Reliability
If conventional theoretical limits are accepted for subthreshold swing, then design expectations are manageable, but TFT leakage cannot be reduced below 60 millivolts per decade
Solution Approach 1:
By dividing the gate control into two separate gates positioned on opposite sides of the channel, the patent achieves better electrostatic control and reduced subthreshold swing. The segmented gate structure allows the electric field to penetrate the channel more effectively from both directions, enabling subthreshold swing values below the conventional 60 mV/decade limit while using standard fabrication processes
Solution Approach 2:
The patent changes the critical parameter of gate control geometry by introducing the double-gate configuration with a thin channel material layer. This parameter change fundamentally improves the electrostatic control mechanism, allowing the TFT to achieve superior subthreshold swing performance (below 60 mV/decade) without requiring exotic or overly complex fabrication processes
Data Source
AI summary
Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.