Double-Gate Thin Film Transistors for Subthreshold Swing Control

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Solution Overview

Problem

Conventional thin film transistors face challenges in scaling down to smaller dimensions due to limitations in subthreshold swing and variability in fabrication processes, making it difficult to extend their performance into the 10 nm or sub-10 nm range, necessitating new methodologies or technologies for future technology nodes.

Innovation Solution

The introduction of double gate thin film transistors with a second gate on top of the channel material layer to improve electrostatic gate control and ON/OFF ratio, and the use of non-planar architectures to increase effective gate width and drive strength, enhancing performance and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional single-gate transistor structures are used, then fabrication processes are simpler and manufacturing is easier, but gate control is insufficient and subthreshold swing cannot be improved below the theoretical limit

Engineering Contradiction:
Improvegate controlVSAvoidtransistor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transistor gate is segmented into two separate gates (first gate and second gate) positioned at opposite sides of the channel. This segmentation allows independent control of the channel from both sides, improving electrostatic control and subthreshold swing performance while maintaining a relatively simple planar structure that is compatible with conventional fabrication processes

Inventive Principle:
Principle #1Segmentation

2Productivity

If transistor dimensions are scaled down to increase density, then more devices fit on chip, but fabrication process variability increases and performance control becomes difficult

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication process control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The invention changes the electrical parameters of the transistor by introducing a second gate that can independently control the channel. This allows tuning of the threshold voltage and subthreshold swing through the second gate voltage, providing an additional degree of freedom to optimize device performance and compensate for fabrication variations even at scaled dimensions

Inventive Principle:
Principle #35Parameter changes

3Reliability

If conventional single-gate structures are used, then device complexity is lower, but ON/OFF ratio and performance are limited

Engineering Contradiction:
ImproveON/OFF ratioVSAvoidgate configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate function is segmented between two independent gates positioned at opposite sides of the channel. The first gate provides basic control while the second gate enhances the ON/OFF ratio by providing additional control over the channel conductivity, achieving superior performance without requiring complex three-dimensional structures

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dual-gate configuration provides multi-functionality where the first gate can control basic operation and the second gate can independently adjust threshold voltage and enhance switching characteristics. This universal control mechanism improves ON/OFF ratio while maintaining compatibility with standard fabrication processes

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12125917B2Thin film transistors having double gates
Publication Date: 2024.10.22 INTEL CORP
  • US12125917B2 patent drawing
  • US12125917B2 patent drawing
  • US12125917B2 patent drawing

AI summary

Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.