Double Gate Thin Film Transistor for High Resolution OLED Displays
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Solution Overview
Problem
Existing organic light emitting diode displays face challenges in achieving high resolution and minimizing space occupied by thin film transistors, while maintaining efficient charge mobility and reducing leakage current.
Innovation Solution
A double gate type thin film transistor design is implemented, featuring a semiconductor with overlapping channel regions and source/drain regions, connected via contact holes through multiple insulating layers, allowing for two transistors to be formed on a single semiconductor with optimized electrode positioning and signal separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single gate thin film transistor design is used, then the transistor structure is simple, but the charge mobility is insufficient and leakage current is high
Solution Approach 1:
The transistor is divided into two separate gate structures (first gate electrode and second gate electrode) that independently control different channel regions. This segmentation allows each gate to optimize charge transport in its respective channel, improving overall charge mobility while maintaining manageable structural complexity through modular design
Solution Approach 2:
The patent introduces a dual-gate configuration where the second gate electrode is positioned above the first gate electrode in the vertical dimension. This three-dimensional arrangement enables independent control of channel regions from different spatial perspectives, enhancing charge mobility through multiple transport pathways without significantly increasing planar footprint
2Manufacturing precision
If transistor size is reduced for high resolution displays, then display resolution improves, but leakage current increases
Solution Approach 1:
By segmenting the channel into two independently controlled regions by separate gates, the patent enables precise control of current flow in each segment. This allows the transistor to maintain low leakage current even when miniaturized for high-resolution displays, as each gate can independently optimize its channel region
Solution Approach 2:
The dual gate structure enables independent adjustment of electrical parameters (such as gate voltage, channel width, and threshold voltage) for each channel region. This parameter optimization allows the transistor to achieve low leakage current while maintaining the small size required for high-resolution display applications
3Reliability
If dual gate structure is implemented, then charge mobility increases, but transistor area increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking the second gate electrode above the first gate electrode. This three-dimensional configuration enables dual-gate functionality without proportionally increasing the planar area, as the gates occupy different vertical levels rather than requiring additional horizontal space
Solution Approach 2:
The patent merges the functionality of two gates into a compact integrated structure where the first and second gate electrodes, along with their respective insulating layers and channel regions, form a unified transistor device. This merging achieves high charge mobility while minimizing the overall transistor footprint for display applications
Data Source
AI summary
A thin film transistor including a substrate; a first gate electrode on the substrate; a first insulating layer covering the substrate and the first gate electrode; a semiconductor on the first insulating layer and overlapping the first gate electrode; a second insulating layer covering the first insulating layer and the semiconductor; a second gate electrode on the second insulating layer and crossing the first gate electrode in plane; a third insulating layer covering the second gate electrode and the second insulating layer; a first source electrode and a first drain electrode on the third insulating layer and connected to the semiconductor; and a second source electrode and a second drain electrode on a same layer as the first source electrode and the first drain electrode and connected to the semiconductor.