Double-Gate TMD Transistor Layout for Switchable NAND/NOR Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-density electronic components due to reduced minimum feature sizes, which complicates the implementation of switchable NAND and NOR logic functions in a single device without requiring complex voltage rematching processes.
Innovation Solution
The development of double-gate and triple-gate transistor devices using a two-dimensional (2-D) material channel, specifically transition metal dichalcogenide (TMD) layers, allows for switchable NAND and NOR logic computing in a single device, simplifying logic gate layout and enhancing area efficiency by enabling voltage rematching or input selection between logic functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines multiple logic gate functions (NAND and NOR) into a single transistor device by utilizing multiple gate electrodes (double-gate or triple-gate configuration) that can be independently controlled. This merging approach increases functional integration density while avoiding the need for separate dedicated transistors for each logic function, thereby reducing overall device complexity despite the reduced feature size
Solution Approach 2:
The transistor device is designed with multi-functionality to perform both NAND and NOR logic operations within a single device structure. By implementing voltage rematching circuits that can switch between different logic modes, the device achieves universal applicability for multiple logic functions, improving integration density without proportionally increasing device complexity
2Area of stationary object
If multiple logic functions are integrated in a single device, then area efficiency improves, but device complexity increases due to voltage rematching requirements
Solution Approach 1:
The patent introduces voltage rematching circuits as intermediary components that facilitate switching between NAND and NOR logic functions. These intermediary circuits manage the voltage level translations and logic mode switching, thereby enabling area-efficient multi-function integration while containing the complexity within dedicated voltage rematching modules rather than dispersing it throughout the entire device structure
3Area of stationary object
If double-gate transistor structure is used to enable logic function switching, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The transistor structure is segmented into multiple gate electrodes (first gate electrode and second gate electrode) that can be independently formed and controlled. This segmentation allows for modular manufacturing processes where each gate can be fabricated and aligned separately, reducing the overall manufacturing precision requirements compared to forming a single complex multi-functional gate structure
Data Source
AI summary
In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.