Double Gate Transistor Heat Dispersion for EPD Stability
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Solution Overview
Problem
Electrophoretic display (EPD) devices face operational abnormalities due to heat generation caused by high voltages applied to pixel transistors, leading to characteristic issues and potential burnout of organic insulating films.
Innovation Solution
A display device with a pixel transistor featuring a double gate structure, where the source and drain electrodes are formed in different layers, overlapping and covering specific channel regions to disperse heat generated by high voltage driving, thereby reducing heat transfer to the organic insulating film and preventing burnout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage is applied to the pixel transistor to drive the electrophoretic display, then the display function is achieved, but heat generation occurs causing characteristic abnormality and operation abnormality
Solution Approach 1:
The pixel transistor is divided into multiple channel regions (first channel region, second channel region, third channel region) with corresponding gate electrodes (first gate electrode, second gate electrode, third gate electrode). This segmentation distributes the voltage application across multiple segments, preventing concentration of heat in a single channel region and thereby reducing overall heat generation while maintaining display functionality.
2Power
If high voltage is applied to the pixel transistor, then the electrophoretic display operates, but organic insulating film burnout occurs due to heat generation
Solution Approach 1:
The pixel transistor channel is segmented into multiple regions with separate gate electrodes, distributing the electrical stress and heat generation across multiple isolated regions. This prevents any single organic insulating film region from being exposed to excessive heat and voltage concentration, thereby preventing burnout and improving reliability.
Solution Approach 2:
The multiple gate electrodes act as intermediary elements between the voltage source and the channel, allowing voltage to be applied in a distributed manner. This intermediary structure prevents direct concentration of high voltage and heat at any single point, protecting the organic insulating film from burnout.
3Device complexity
If conventional single gate structure is used, then device complexity is low, but heat dispersion capability is insufficient under high voltage driving
Solution Approach 1:
The transistor structure is segmented into multiple channel regions with corresponding gate electrodes, transforming a simple single-gate structure into a multi-gate structure. This segmentation significantly enhances heat dispersion capability by distributing heat generation across multiple spatially separated regions, while the added complexity remains manageable through systematic arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double gate structure effectively disperses heat generated by high voltage operation, reducing the risk of organic insulating film burnout and improving the transistor's voltage withstand capability, ensuring stable operation of the EPD device.
Implementation Method 1
The source electrode is formed to cover at least a first channel region in planar view. The drain electrode is formed to cover at least a second channel region in planar view... effectively disperses heat generated by high voltage operation, reducing the risk of organic insulating film burnout
Data Source
AI summary
According to one embodiment, a display device includes a display panel and a drive circuit. A transistor provided in a pixel portion or a peripheral portion of the display panel includes a semiconductor layer having a first end and a second end, first and second gate electrodes overlapping the semiconductor layer, a source electrode connected to the first end, and a drain electrode connected to the second end. The first and second gate electrodes are disposed in a first layer. The source electrode and the drain electrode are disposed in a second layer. The source electrode is formed to cover at least a first channel region in planar view. The drain electrode is formed to cover at least a second channel region in planar view.