Double-Gate Transistor High-K Dielectric Leakage Control
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Solution Overview
Problem
As transistors scale below 100 nm, conventional silicon dioxide gate dielectrics fail to provide sufficient electrical isolation, leading to increased transistor leakage current and power dissipation, while existing high-K dielectric materials face material quality and interface issues, and dopant poisoning affects transistor performance.
Innovation Solution
A planar double-gate transistor structure with high-K rare-earth dielectric layers and single-crystal semiconductor layers, deposited via epitaxy, which maintains single-phase morphology and high-quality interfaces, mitigating short-channel effects and floating body issues, and is compatible with conventional processing methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon dioxide gate dielectric is used, then manufacturing simplicity is maintained, but electrical isolation becomes insufficient leading to increased leakage current
Solution Approach 1:
The patent changes the dielectric constant parameter by transitioning from conventional silicon dioxide (K≈3.9) to high-K rare-earth dielectric materials (K>10). This parameter change enables sufficient electrical isolation and reduced leakage current while maintaining reasonable dielectric thickness, directly resolving the contradiction between maintaining manufacturing simplicity and achieving adequate electrical isolation.
Solution Approach 2:
The patent employs composite material structures combining rare-earth dielectric layers with semiconductor layers, creating a high-K metal oxide semiconductor (HKMOS) system. This composite approach achieves superior electrical isolation properties while managing interface quality and mitigating dopant poisoning effects through carefully designed material combinations.
2Reliability
If high-K dielectric materials are used, then electrical isolation improves, but material quality and interface issues arise
Solution Approach 1:
The patent introduces carefully engineered interface layers and transition structures between the high-K rare-earth dielectric and semiconductor layers. These intermediary structures mitigate interface quality issues and dopant poisoning effects, enabling the benefits of high-K materials to be realized while managing the challenges of material compatibility and interface integrity.
Solution Approach 2:
The patent applies different material compositions and structural characteristics at different locations within the gate stack. By optimizing the local quality of dielectric layers, interface regions, and gate conductor materials separately, the patent achieves both high electrical isolation and acceptable interface quality, resolving the contradiction between these two requirements.
3Productivity
If gate length is reduced below 100 nm, then transistor scaling progress is achieved, but substrate effects and physical limitations become severe
Solution Approach 1:
The patent transitions from planar single-gate structures to vertical multi-gate structures (double-gate, triple-gate, or surround-gate configurations). This dimensional change provides enhanced electrostatic control over the channel at scaled dimensions, mitigating short-channel effects while maintaining continued transistor scaling progress.
Solution Approach 2:
The patent segments the gate structure into multiple gates (double-gate or triple-gate configurations) that control the channel from different spatial locations. This segmentation provides superior electrostatic control compared to a single planar gate, enabling reliable operation at gate lengths below 100 nm by counteracting substrate effects and short-channel phenomena.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables transistors with improved operation and reduced leakage current, maintaining high performance even at small gate lengths, and addresses the limitations of conventional silicon dioxide and high-K dielectric materials by providing robust electrical circuits with high-quality dielectric/semiconductor interfaces.
Implementation Method 1
Each of the upper and lower gate stacks comprise a high-K gate dielectric that is a rare-earth dielectric having a single-phase crystal structure
Implementation Method 2
deposited via epitaxy, which maintains single-phase morphology and high-quality interfaces
Data Source
AI summary
A planar, double-gate transistor structure comprising upper and lower gate stacks that each comprises a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics having gate-lengths less than 65 nm.