Double Gate Transistor Device for Power Switching
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Solution Overview
Problem
Field-effect controlled power transistor devices face challenges in robustness against parasitic voltage spikes and efficient switching operations due to rapid current changes during switching operations in power circuits.
Innovation Solution
A double gate transistor device with two gate electrodes, each dielectrically insulated from the body region, allows for independent control of conducting channels to switch the device on and off efficiently, reducing parasitic capacitance and electromagnetic interference by generating and interrupting conducting channels in a controlled manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single gate electrode is used in conventional power transistors, then the device structure is simple, but the device is vulnerable to parasitic voltage spikes and switching efficiency is limited
Solution Approach 1:
The single gate electrode is segmented into two separate gate electrodes (first gate electrode and second gate electrode) that are dielectrically insulated from the body region. This segmentation allows independent control of conducting channels, enabling the first gate to handle switching operations while the second gate suppresses parasitic voltage spikes, thereby resolving the contradiction between reliability improvement and structural complexity.
Solution Approach 2:
A separation layer is introduced as an intermediary element between the first gate electrode and the second gate electrode. This separation layer provides dielectric insulation while maintaining compact spacing, enabling the two gates to function independently without requiring excessive space or complex interconnection structures, thus managing the device complexity while achieving enhanced reliability.
2Area of stationary object
If gate electrodes are placed close together to reduce device area, then area is reduced, but parasitic capacitance between gates increases
Solution Approach 1:
A separation layer with specific dielectric properties is positioned between the first gate electrode and the second gate electrode. This intermediary layer enables the gates to be placed in close proximity (reducing device area) while the dielectric material properties are selected to minimize parasitic capacitance, thus resolving the contradiction between area reduction and parasitic capacitance control.
Solution Approach 2:
The dielectric properties of the separation layer are optimized to achieve low parasitic capacitance. By changing the dielectric constant and thickness parameters of the separation layer, the design achieves compact gate spacing without significant parasitic capacitance increase, resolving the area versus parasitic capacitance contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double gate transistor device effectively mitigates parasitic voltage spikes and ensures efficient switching with reduced electromagnetic interference, enhancing the reliability and performance of power transistor operations.
Implementation Method 1
switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode
Implementation Method 2
generating a second conducting channel in the body region by driving a second gate electrode
Implementation Method 3
The first gate electrode is dielectrically insulated from a body region by a first gate dielectric
Implementation Method 4
The second gate electrode is dielectrically insulated from the body region by a second gate dielectric
Data Source
AI summary
In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.