Double Gate Transistors with Segmented Polysilicon for Threshold Stability
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Solution Overview
Problem
Transistors with vertical channels in semiconductor memory devices face challenges in maintaining a stable threshold voltage due to the short channel effect caused by reduced thickness of the active region, leading to decreased charge mobility and increased power consumption.
Innovation Solution
The implementation of double gate transistors with at least two polysilicon patterns on a thin body active region, where the polysilicon patterns have different crystalline structures and impurity concentrations, and are stacked with a gate insulating pattern covering the top surface and sidewall, allowing for adjustable threshold voltage without ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the top surface width of the active region is reduced to increase integration density, then the integration density increases, but the thickness of the thin body decreases causing short channel effect and threshold voltage instability
Solution Approach 1:
The gate structure is segmented into two separate gates (first gate and second gate) positioned at opposite sides of the thin body active region. This segmentation allows each gate to independently control the channel, providing better electrostatic control and preventing short channel effects even when the thin body thickness is reduced for high integration density.
Solution Approach 2:
A gate insulating layer is introduced as an intermediary between the gate electrodes and the thin body active region. This intermediary layer enables effective electrical control of the channel while electrically isolating the gates from direct contact with the active region, allowing threshold voltage stabilization without requiring larger device dimensions.
2Reliability
If impurity ions are implanted to prevent short channel effect, then the threshold voltage stability improves, but the charge mobility degrades
Solution Approach 1:
The patent replaces the mechanical/chemical approach of impurity ion implantation with an electrical field-based approach using double gate control. By applying appropriate voltages to the two gates, the threshold voltage can be adjusted and short channel effects suppressed without introducing impurity ions that would scatter charge carriers and reduce mobility.
3Productivity
If the channel width is reduced to increase integration density, then the integration density increases, but the power consumption increases due to threshold voltage instability
Solution Approach 1:
The double gate structure provides dynamic control of the threshold voltage through independent voltage application to each gate. This dynamic adjustability allows the device to maintain optimal threshold voltage levels even with reduced channel dimensions, preventing the leakage currents and power consumption increases that would otherwise result from threshold voltage instability in high-density configurations.
Data Source
AI summary
Double gate transistors having at least two polysilicon patterns on a thin body used as an active region and methods of forming the same are provided. Embodiments of the transistors and methods provided are capable of enhancing current drivability of a semiconductor memory device using polysilicon patterns having different impurity concentrations from each other. In some embodiments an active region is protruded from a semiconductor substrate, an impurity diffusion region is formed in the active region, and a gate insulating pattern and a gate pattern are sequentially stacked on the active region. In these embodiments, the gate pattern may include polysilicon patterns having different impurity concentrations from each other.