Double-Gated FeFET Memory Cell for Read-Write Separation
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Solution Overview
Problem
Ferroelectric field-effect transistors (FeFETs) face challenges such as poor sense margin due to compromised gate dielectric interfaces, requiring higher coercive fields, slow read operations, and the inability to perform simultaneous read and write operations, which limits their effectiveness in memory applications.
Innovation Solution
A double-gated ferroelectric field-effect transistor (FeFET) design is implemented, where a ferroelectric material is incorporated into one gate oxide layer, allowing independent control of both gates, enabling concurrent write and erase operations and mitigating depolarization fields, thus improving short-channel control and current on-off ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-gate FeFET structure is used, then the device complexity is low, but the sensing margin is poor due to compromised gate dielectric interfaces
Solution Approach 1:
The single gate structure is segmented into two independent gates (first gate electrode and second gate electrode), each capable of independent control. This segmentation allows separate optimization of write and read operations, improving the sensing margin while maintaining reasonable device complexity through systematic design
2Device complexity
If a single gate controls both read and write operations, then the device complexity is low, but simultaneous read and write operations cannot be performed
Solution Approach 1:
The control function is segmented by providing two independent gates that can be controlled by separate wordlines. This enables parallel operation where one gate handles write operations while the other handles read operations, doubling the operational throughput without significantly increasing overall device complexity
Solution Approach 2:
The gate control system is made dynamic by enabling independent voltage application to each gate. The first gate can be programmed to a first voltage state while the second gate is programmed to a second voltage state, allowing flexible and simultaneous execution of different operations
3Reliability
If higher coercive fields are applied to overcome interface issues, then the reliability of data storage is improved, but the energy consumption increases
Solution Approach 1:
The electric field distribution is optimized locally by applying different voltages to different gates. The first gate electrode can apply a higher voltage to ensure reliable write operations and overcome interface issues, while the second gate electrode operates at lower voltages for efficient read operations, reducing overall energy consumption while maintaining data storage reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double-gated FeFET enhances memory performance by allowing independent read and write operations, boosting write fields, and reducing the need for additional transistors, leading to improved sensing margins and efficient data storage.
Implementation Method 1
a ferroelectric material is incorporated into one gate oxide layer
Data Source
AI summary
A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.