Double-Gated Non-Volatile Memory FDSOI Transistor Integration
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Solution Overview
Problem
Integration of non-volatile memory elements with Fully Depleted Semiconductor-on-Insulator (FDSOI) transistors is complicated, and hot carrier injection programming requires a body tie to prevent undesired charge accumulation in the channel region, necessitating improved FDSOI transistors for use in non-volatile memory.
Innovation Solution
A method for forming a semiconductor device involves bonding two wafers with a storage layer between the semiconductor structure and gate material, cleaving to create a channel region, and patterning to form a double-gated transistor with a bottom gate and top gate, allowing for effective programming and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If hot carrier injection programming is used to program NVM elements with FDSOI transistors, then programming capability is achieved, but undesired charge accumulation occurs in the channel region
Solution Approach 1:
The patent extracts the body region from the traditional FDSOI transistor structure by removing the semiconductor substrate beneath the channel, leaving only the thin film semiconductor layer. This extracted body region is then independently controlled through a dedicated body contact, allowing separate control of the channel region charge without affecting the main transistor operation, thus preventing charge accumulation during hot carrier injection programming
Solution Approach 2:
The patent introduces an intermediary body contact that mediates between the channel region and the external circuit. This body contact serves as an intermediate control point that can independently adjust the potential of the body region, enabling precise control of charge distribution in the channel during programming operations without direct interference with the source-drain current path
2Reliability
If a body tie is added to prevent charge accumulation, then charge control is improved, but device complexity increases
Solution Approach 1:
The patent merges the body region control function with the existing FDSOI transistor structure by utilizing the naturally occurring thin film semiconductor layer as the body region. The body contact is integrated into the same planar structure as the source and drain contacts, creating a unified device layout that provides charge control without adding significant structural complexity or requiring separate three-dimensional components
3Adaptability or versatility
If non-volatile memory elements are integrated with FDSOI transistors, then memory functionality is achieved, but integration complexity increases
Solution Approach 1:
The patent creates a universal transistor structure that can function both as a standard FDSOI transistor for logic operations and as a non-volatile memory element. The thin film semiconductor layer with controlled body potential serves dual purposes: enabling normal transistor operation when biased conventionally and enabling hot carrier injection programming when appropriate voltages are applied to the body contact, thus providing multi-functionality without requiring separate dedicated structures for each mode
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of improved FDSOI transistors suitable for non-volatile memory, facilitating efficient programming and reducing unwanted charge accumulation, thereby enhancing the integration of non-volatile memory elements.
Implementation Method 1
bonding a first side of the second wafer to the first wafer
Data Source
AI summary
A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.