Double Gated Thin Film Transistors for Sub-10 nm Leakage Control
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling down multi-gate transistors to sub-10 nm dimensions due to limitations in subthreshold swing and variability, which hampers the integration of high-density, high-performance devices in future technology nodes.
Innovation Solution
The implementation of double-gated thin film transistors with a three-dimensional metal template as a bottom gate electrode and independent operation of bottom and top gate electrodes to dynamically adjust threshold voltage and leakage current, enhancing gate control and reducing leakage power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication processes are used for multi-gate transistors, then manufacturing cost and compatibility with existing infrastructure are reduced, but device performance and subthreshold swing are limited
Solution Approach 1:
The transistor gate is segmented into two independent gates (first gate electrode and second gate electrode) that can be controlled separately. This allows independent optimization of different transistor functions: one gate controls threshold voltage while the other controls leakage current, thereby improving device performance without requiring complete process overhaul
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional structures with gates positioned at both top and bottom surfaces. This dimensional change enables superior electrostatic control and improved subthreshold swing characteristics while maintaining compatibility with existing fabrication processes
2Productivity
If transistor dimensions are scaled down to sub-10 nm, then device density is increased, but fabrication variability and process constraints worsen
Solution Approach 1:
The patent implements dynamically controllable threshold voltages through independent gate control. By adjusting the voltage on the first gate electrode, the threshold voltage can be tuned to optimize device operation at different technology nodes, compensating for fabrication variability and enabling reliable operation at sub-10 nm dimensions
Solution Approach 2:
The patent utilizes adjustable electrical parameters (gate voltages) to optimize transistor performance. By changing the voltage applied to the first gate electrode, the threshold voltage can be dynamically adjusted to account for process variations, thereby maintaining manufacturing precision even as dimensions scale down
3Device complexity
If single gate structures are used, then device complexity is reduced, but gate control and leakage management are insufficient
Solution Approach 1:
The gate structure is divided into two independent gate electrodes that can be controlled separately. This segmentation allows one gate to optimize for threshold voltage control while the other gate manages leakage current, achieving superior gate control without excessive complexity
Solution Approach 2:
The dual gate structure provides multi-functionality: the first gate electrode handles threshold voltage control while the second gate electrode handles leakage current management. This universal design approach allows a single device structure to perform multiple critical functions that would otherwise require separate components
Data Source
AI summary
Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.