Double Gated Vertical Select Devices for Leakage Current Reduction
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Solution Overview
Problem
Existing non-volatile memory arrays face challenges in reducing leakage currents and manufacturing complexity due to the need for diodes in series with variable resistive elements, which complicates operations and increases power consumption.
Innovation Solution
A three-dimensional memory array architecture with vertically oriented select devices that eliminate the need for diodes by using double gated vertically oriented select devices connected to bit and global bit lines, allowing direct communication between them, thereby reducing leakage currents and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If diodes are connected in series with variable resistive elements to reduce leakage currents, then leakage current is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent removes diodes from the memory cell structure entirely, extracting the harmful element that caused both leakage current and device complexity. Instead of adding diodes in series with variable resistive elements, the invention uses a vertical transistor architecture where the transistor itself provides the necessary switching and isolation functions, eliminating the need for separate diode components.
Solution Approach 2:
The vertical transistor serves multiple functions simultaneously: it acts as a select device, provides isolation, controls current flow, and enables memory operations. This multi-functional component replaces what would otherwise require separate diodes and select transistors, reducing overall device complexity while maintaining leakage current control.
2Object-generated harmful factors
If diodes are connected in series with variable resistive elements to reduce leakage currents, then leakage current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent eliminates diodes from the manufacturing process entirely. The vertical transistor architecture can be fabricated using standard CMOS or TFT processes without requiring additional diode formation steps, ion implantation for diode junctions, or separate diode alignment and integration processes, thereby simplifying manufacturing.
Solution Approach 2:
The invention changes the fundamental architectural parameter from a planar cross-point structure with series diodes to a vertical transistor structure. This parameter change enables the use of existing transistor fabrication processes rather than requiring complex diode integration processes, improving ease of manufacture.
3Productivity
If voltages are applied to a large number of memory elements in parallel for data reading and programming, then productivity increases, but power consumption increases due to leakage currents
Solution Approach 1:
The patent converts the potentially harmful leakage current into a beneficial feature by using the vertical transistor's channel to control current flow. The transistor channel, which would normally be a source of leakage, becomes the controlled path for desired current during read and program operations, enabling parallel operations with reduced unwanted leakage.
Solution Approach 2:
The vertical transistor acts as an intermediary between the bit line and word line, controlling current flow to selected memory elements while blocking current to unselected elements. This intermediary function enables parallel operations on multiple memory elements without the excessive power consumption that would result from leakage currents flowing through all elements connected to the same bit and word lines.
Data Source
AI summary
A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.