Double Hard Mask Structure for Semiconductor Gate Protection
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Solution Overview
Problem
In the semiconductor industry, the conventional single-material hard mask used in the self-aligned contact process is prone to removal during contact plug formation, leading to short circuits between gate and source/drain regions due to boron penetration and depletion effects, which degrade device performance.
Innovation Solution
A method involving the formation of two-layered hard masks, where a first hard mask of silicon nitride is adjacent to and surrounds a second hard mask of silicon oxide, ensuring they are coplanar with the interlayer dielectric layer, preventing contact plug shorts and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-material hard mask is used during self-aligned contact process, then the fabrication process is simple, but the hard mask is easily removed during contact plug formation causing short circuits
Solution Approach 1:
The single hard mask layer is divided into two distinct hard mask layers with different materials and etch resistances. The first hard mask layer has higher etch resistance to prevent removal during contact plug formation, while the second layer provides the necessary patterning function, thereby resolving the contradiction between process simplicity and contact plug integrity.
Solution Approach 2:
Two different hard mask materials are combined in a layered structure, where each material is selected for its specific etch resistance properties. This composite structure provides both the protection needed during contact plug formation and the patterning capability required for fabrication, addressing both reliability and ease of manufacture concerns.
2Manufacturing precision
If the hard mask is removed during contact plug formation, then the contact plug can reach the source/drain region, but short circuits occur between gate and source/drain
Solution Approach 1:
The first hard mask layer is strategically positioned and designed with higher etch resistance specifically at critical regions where electrical isolation is needed. This localized enhancement of etch resistance prevents unwanted removal at the gate region while allowing controlled removal elsewhere, maintaining both contact plug positioning accuracy and electrical isolation.
3Ease of manufacture
If polysilicon gate is used, then the gate structure is simple to fabricate, but boron penetration and depletion effects degrade device performance
Solution Approach 1:
The gate material is changed from polysilicon to metal, fundamentally altering the electrical and physical parameters of the gate structure. This material substitution eliminates boron penetration and depletion effects while maintaining fabricability through the self-aligned contact process, thereby resolving the contradiction between fabrication simplicity and device performance.
Data Source
AI summary
A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.