Standard Cell Layout with Double Height Cells for IC Density
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Solution Overview
Problem
Current standard cell designs for integrated circuits face challenges in optimizing packing density, power consumption, and area efficiency, particularly in balancing the layout and performance between single height and double height cells.
Innovation Solution
The integrated circuit design incorporates alternating rows of N-wells and P-wells with standard cells of varying heights, where double height cells are strategically placed to enhance packing density, power reduction, and high-speed operation, while maintaining area efficiency by optimizing transistor and doping region dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells are arranged in fixed-height rows with alternating N-wells and P-wells, then layout regularity and manufacturing ease are improved, but packing density and area efficiency deteriorate
Solution Approach 1:
The standard cell is divided into two distinct height types: single-height cells (one row height) and double-height cells (two rows height). This segmentation allows flexible arrangement where double-height cells can span across two alternating well rows (N-well and P-well), thereby improving packing density without compromising the regular alternating well structure that ensures manufacturing ease.
2Area of stationary object
If double height cells are used to improve packing density, then area efficiency is improved, but design complexity and layout optimization difficulty worsen
Solution Approach 1:
The patent establishes universal design rules that allow both single-height and double-height cells to follow the same alternating N-well/P-well structure. Double-height cells are designed to accommodate both NMOS and PMOS transistors across two well rows, providing multi-functionality. This universal approach maintains design regularity while improving area efficiency, thereby reducing design complexity despite the presence of varying cell heights.
3Speed
If alternating N-wells and P-wells are used, then transistor performance and speed are improved, but area consumption increases
Solution Approach 1:
The patent merges single-height and double-height cells in the same standard cell library, where double-height cells utilize both N-well and P-well rows within their structure. This merging allows more transistors to be packed into a given area while maintaining the alternating well structure, thereby improving area efficiency without sacrificing the speed benefits provided by the alternating N-well/P-well configuration.
Data Source
AI summary
An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.