Double-Height TAP Cell Grid for Latch-Up Immunity

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Solution Overview

Problem

The placement of TAP cells in integrated circuit (IC) layouts faces challenges such as process bottlenecks due to reduced lithography critical dimensions and mixed channel effects, particularly at advanced manufacturing nodes, which affect latch-up immunity and well tap resistance.

Innovation Solution

TAP cells are arranged in an interleaving manner in two transverse directions with a double cell height, alternating between different types, and are configured to collect body currents from wider areas, reducing well tap resistance and improving latch-up immunity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If TAP cells are placed using conventional methods at advanced manufacturing nodes, then lithography critical dimensions are reduced, but process bottlenecks occur and latch-up immunity deteriorates

Engineering Contradiction:
Improvelithography critical dimensionVSAvoidlatch-up immunity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent transitions from conventional single-row TAP cell placement to a two-dimensional interleaved grid pattern, where first and second TAP cells are arranged in alternating rows and columns. This spatial reconfiguration in multiple dimensions allows maintenance of adequate spacing for latch-up immunity while accommodating reduced lithography dimensions at advanced manufacturing nodes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The TAP cell structure is segmented into two distinct types (first TAP cells and second TAP cells) with different orientations and placements. This segmentation allows the system to distribute current collection functions across multiple separated elements rather than relying on single large structures, resolving the conflict between small dimensions and reliability.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If conventional TAP cell placement is used, then layout simplicity is maintained, but well tap resistance increases and current collection efficiency decreases

Engineering Contradiction:
Improvelayout simplicityVSAvoidwell tap resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent extends TAP cell current collection from one-dimensional linear arrangements to two-dimensional interleaved patterns, where current is collected through multiple pathways in both horizontal and vertical directions. This dimensional expansion reduces equivalent resistance by providing parallel current collection routes without significantly increasing layout complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent combines first TAP cells and second TAP cells into a unified interleaved structure that works together as an integrated current collection system. The merging of these complementary structures creates a more efficient overall system with reduced resistance compared to separate conventional placements.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If TAP cell area is reduced to increase density, then more cells can be placed, but latch-up immunity and current collection efficiency worsen

Engineering Contradiction:
ImproveTAP cell areaVSAvoidlatch-up immunity
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies different characteristics to different locations in the array, with first TAP cells and second TAP cells having complementary orientations and properties. This local differentiation allows each cell to contribute optimally to current collection in its specific location while maintaining overall latch-up immunity through the distributed pattern.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

By arranging TAP cells in a two-dimensional interleaved pattern rather than reducing individual cell size, the patent maintains adequate area for each cell's latch-up protection function while increasing overall density through more efficient spatial utilization in multiple directions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12520579B2Method and system for manufacturing integrated circuit device
Publication Date: 2026.01.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12520579B2 patent drawing
  • US12520579B2 patent drawing
  • US12520579B2 patent drawing

AI summary

A method includes forming, over a substrate, a plurality of well taps arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps is arranged at intervals in a first direction and a second direction transverse to the first direction. The plurality of well taps includes at least one first well tap. The forming the plurality of well taps comprises forming the first well tap by forming a first well region of a first type. The first well region comprises two first end areas and a first middle area arranged consecutively between the two first end areas in the second direction. The forming the first well tap further comprises implanting, in the first middle area, a first dopant of a first type, and implanting, in the first end areas, a second dopant of a second type different from the first type.