Double Hybrid Bonded Die Stacking for Contamination-Limited Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in die stacking for electronic devices is the contamination and reduced connection efficiency due to surface residue, which limits the surface area available for hybrid bonding, affecting the performance and yield of computing devices.
Innovation Solution
The implementation of a double hybrid bonding method using a combination of first and second hybrid bond layers with misaligned metal pads to increase the surface area for electrical connections, enhancing the alignment and contact between semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional single hybrid bonding is used, then the manufacturing process is simple, but the surface area for electrical connections is limited and contamination affects yield
Solution Approach 1:
The bonding process is divided into two separate hybrid bonding operations: a first hybrid bonding step that bonds the first semiconductor die to the second semiconductor die, and a second hybrid bonding step that bonds the third semiconductor die to the bonded structure. This segmentation allows each bonding step to be optimized independently, improving alignment precision and connection efficiency while managing contamination risks through staged processing
Solution Approach 2:
The patent extends the bonding interface from a single plane to multiple planes by performing hybrid bonding at different stages. The first hybrid bond layer creates connections on a first bonding surface, while the second hybrid bond layer creates additional connections on a second bonding surface, effectively utilizing multiple dimensional layers for electrical connections and maximizing the total bonding area
2Speed
If more interconnects are positioned on the exterior surface, then data transmission speed increases, but the surface area available for bonding decreases due to contamination
Solution Approach 1:
The invention utilizes multiple bonding surfaces and layers to increase the effective bonding area. By performing first and second hybrid bonding operations at different stages and locations, the patent creates additional bonding interfaces that extend beyond the limitations of a single surface, thereby providing sufficient area for both high-density interconnects and reliable bonding
Solution Approach 2:
The first hybrid bonding step is performed before the second hybrid bonding step, establishing initial connections and creating a stable bonded structure. This preliminary bonding action allows subsequent processing and positioning of additional dies without compromising the integrity of earlier bonds, enabling progressive buildup of complex multi-die structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical connection efficiency between semiconductor dies, enabling faster data transmission and increased computing performance by maximizing the surface area for hybrid bonding, thus addressing the contamination and yield issues.
Implementation Method 1
a hybrid bond layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling ones of the first metal pads to respective ones of the second metal pads
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Systems, apparatus, and articles of manufacture are disclosed to enable integrated circuit packages with double hybrid bonded dies and methods of manufacturing the same include an integrated circuit (IC) package including a first semiconductor die including first metal vias spaced apart along a first layer of a first dielectric material, the first metal vias connected to respective first metal pads of the first semiconductor die, a second semiconductor die including second metal pads of the second semiconductor die, and a hybrid bond layer including a third dielectric material and third metal vias spaced apart along the third dielectric material, a subset of the third metal vias electrically coupling ones of the first metal pads to respective ones of the second metal pads, a first one of the third metal vias positioned beyond a lateral side of the first semiconductor die.