Double-Island MOSFET Package for Compact Thermal Isolation
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Solution Overview
Problem
Traditional power MOSFET devices are cumbersome and do not allow integration of two power MOSFET devices together, despite providing optimal heat dissipation and electrical insulation.
Innovation Solution
A power semiconductor device with a double island surface mount package design, featuring a first and second die housed within a package with insulation multilayers and a covering metal layer that electrically couples with conductive contact regions, allowing for integration of two power MOSFET devices while maintaining insulation and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional vertical packages with pins are used for power MOSFET devices, then optimal heat dissipation and high electrical insulation are achieved, but the devices become cumbersome and integration of two power MOSFET devices together is not enabled
Solution Approach 1:
The patent merges two separate power MOSFET devices into a single integrated package structure. The first and second power semiconductor devices are mounted on a common insulating substrate with shared electrical connections and common heat dissipation path, enabling integration while maintaining individual device functionality.
Solution Approach 2:
The insulating substrate serves multiple functions simultaneously: it provides electrical insulation between conductive elements, supports mechanical mounting of both power MOSFET devices, establishes electrical connections between terminals, and acts as a heat dissipation pathway. This multi-functionality reduces overall package complexity.
2Volume of moving object
If two power MOSFET devices are integrated in a single package, then encumbrance is reduced and integration is enabled, but maintaining adequate electrical insulation and heat dissipation becomes challenging
Solution Approach 1:
An insulating substrate is introduced as an intermediary element between the two power MOSFET devices and their electrical connections. This substrate provides adequate electrical insulation while enabling compact integration, acting as a mediator that allows close proximity of conductive elements without compromising insulation reliability.
3Volume of moving object
If two power MOSFET devices are integrated in a single package, then encumbrance is reduced, but ensuring adequate separation between leads connected to terminals becomes difficult
Solution Approach 1:
The patent transitions from vertical lead arrangement to a planar configuration where leads extend from the insulating substrate in different directions. This dimensional change allows adequate lead separation distance to be achieved within a compact package footprint by utilizing lateral spacing rather than vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, efficiently cooled, and electrically insulated package that supports bidirectional AC switches, reducing encumbrance and parasitic effects, with improved thermal efficiency and reduced contact resistance.
Implementation Method 1
a bottom insulation multilayer (16, 26) and a top insulation multilayer (16), respectively arranged underneath and on top of the common heat dissipater (4a)
Implementation Method 2
which carry, respectively, the first and second dice and each include a respective top metal layer (26a, 16a), respectively used for heat dissipation outwards
Implementation Method 3
A covering metal layer (19, 36) is arranged on top of the first and second dice (6, 106) and comprises projecting metal regions (28, 128), which extend into the windows so as to couple electrically with corresponding conductive contact regions
Implementation Method 4
a common heat dissipater (4a), which is arranged on top of the insulating substrate (3) and on which the bottom insulation multilayer (16, 26) and the first and second power semiconductor devices (6, 106) are mounted
Data Source
AI summary
A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.