Double-Layer 3D Fan-Out Packaging Structure for High Integration
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Solution Overview
Problem
Conventional single-layer fan-out wafer-level packaging technologies result in low integration levels and large package volumes, limiting the performance of integrated circuits due to the need for re-packaging multiple chips, which increases the complexity and size of the circuit interconnections.
Innovation Solution
A double-layer packaged 3D fan-out packaging structure is developed, which includes a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, a solder ball bump, and a second packaging material layer, allowing for the stacking of two layers of fan-out wafers in the third-dimensional direction, thereby improving integration and reducing package volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-layer fan-out wafer-level packaging is used, then the packaging process is simple, but the integration level is low and package volume is large
Solution Approach 1:
The patent transitions from single-layer (2D) packaging to double-layer (3D) packaging by stacking fan-out wafers vertically. Multiple chips are packaged in the third dimension, achieving higher integration without significantly complicating the packaging process. The double-layer structure allows chips to be arranged in stacked configurations, improving space utilization and integration level.
2Ease of manufacture
If single-layer fan-out wafer-level packaging is used, then the packaging process is simple, but the package volume is large
Solution Approach 1:
By stacking fan-out wafers in the vertical direction (third dimension), the patent reduces the horizontal footprint of the package. The double-layer configuration allows multiple chips to occupy less planar space, thereby reducing overall package volume while maintaining manufacturing simplicity.
Solution Approach 2:
The patent implements a nested structure where one fan-out wafer is placed on top of another, with lower-layer chips nested within the vertical space occupied by upper-layer chips. This nesting approach maximizes space utilization and reduces the external dimensions of the final package.
3Quantity of substance
If multiple chips are re-packaged to achieve higher density, then circuit interconnection is possible, but the integration level remains low and package volume increases
Solution Approach 1:
The patent performs fan-out wafer formation and chip attachment in advance, creating pre-assembled wafer layers that can be directly stacked. This preliminary action eliminates the need for complex re-packaging operations, as chips are already positioned and connected before the final stacking process. The pre-formed wafer structure simplifies subsequent assembly steps.
Solution Approach 2:
The patent divides the packaging process into independent stages: forming individual fan-out wafers with attached chips, then stacking these pre-formed layers. This segmentation allows each wafer to be processed separately and independently, reducing overall process complexity while achieving high chip density through vertical integration.
Data Source
AI summary
The present disclosure provides a double-layer packaged 3D fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and a second packaging material layer. The formed double-layer packaged 3D fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the integration level of the package and reducing the package volume.