Double-Layer Lead Frame Carrier for Low-Stress Chip Mounting
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Solution Overview
Problem
Conventional optoelectronic semiconductor devices face challenges in efficient electrical connection and thermal management due to differences in thermal expansion coefficients between flip chips and carriers, leading to potential electrical connection breaks and high thermal resistance, especially in miniaturized designs for automotive, consumer electronics, and industrial applications.
Innovation Solution
The use of Routable QFN (Rt-QFN) lead frame-based carriers with separate manufacturing steps for upper and lower metal structures, allowing for smaller structure sizes, floating areas, and reduced mechanical stress, which enables efficient electrical and thermal connectivity without the need for tie bars and minimizes exposure of metallic surfaces, thereby improving reliability and reducing thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional carriers are used with flip chips, then electrical connection can be established, but thermal expansion coefficient differences cause connection breaks and high thermal resistance
Solution Approach 1:
The patent changes the physical parameters of the lead frame by creating a two-layer structure with different thicknesses. The support layer is made thicker than the mounting layer, providing enhanced mechanical stability and thermal management capabilities while maintaining electrical connectivity. This parameter change allows the lead frame to better accommodate thermal expansion differences without breaking electrical connections.
Solution Approach 2:
The patent transitions from a conventional single-layer lead frame to a two-layer lead frame structure. By adding the vertical dimension with a support layer beneath the mounting layer, the invention creates additional structural capacity to handle thermal stresses and improve heat dissipation pathways, thereby reducing thermal resistance while maintaining connection reliability.
2Volume of moving object
If miniaturized designs are implemented, then device size is reduced, but mechanical stress increases and handling becomes difficult
Solution Approach 1:
The patent segments the lead frame into two distinct functional layers: a support layer for mechanical strength and a mounting layer for electrical connectivity. This segmentation allows each layer to be optimized independently - the support layer can be made thicker to provide mechanical strength in miniaturized devices, while the mounting layer maintains the necessary electrical connection features.
Solution Approach 2:
The patent applies different qualities to different parts of the lead frame structure. The support layer is designed with greater thickness for mechanical strength, while the mounting layer is optimized for electrical connectivity. This local differentiation of structural qualities allows miniaturized devices to maintain adequate mechanical strength despite reduced overall size.
3Manufacturing precision
If separate manufacturing steps are used for upper and lower metal structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The manufacturing process is segmented into separate steps for creating the support layer and mounting layer. This segmentation enables precise control over each layer's geometry and properties, achieving high manufacturing precision. The two-layer structure itself is segmented to allow independent optimization of each layer's function.
Solution Approach 2:
The two-layer lead frame structure serves multiple functions simultaneously: the support layer provides mechanical strength and structural stability, while the mounting layer provides electrical connectivity and component mounting surfaces. This multi-functionality justifies the increased structural complexity by delivering enhanced performance across multiple parameters.
Data Source
AI summary
In an embodiment an optoelectronic semiconductor device includes a carrier comprising a mounting side and an attachment side opposite the mounting side, a plurality of separate, metallic lead frame parts and a potting body mechanically holding together the lead frame parts, and a plurality of optoelectronic semiconductor chips mounted on the mounting side, wherein the lead frame parts project beyond the potting body at the mounting side, wherein at least some of the lead frame parts have a double-layered design so that the lead frame parts together form a support layer on the attachment side and a mounting layer on the mounting side, wherein the support layer is embedded in the potting body and the mounting layer extends at least partially onto the potting body.