Double-Layered Network Architecture for Bandwidth Efficiency
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Solution Overview
Problem
Existing network-on-chip (NOC) architectures in integrated circuits face inefficiencies in bandwidth utilization due to the transfer of header and control flits, which consume significant resources in terms of area and power consumption.
Innovation Solution
A double-layered network architecture is introduced, comprising a wide layer that supports packets with headers, control information, and data payloads, and a narrow layer that supports packets with headers and control information only. These layers are asynchronously routed, allowing for more efficient bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-layered NOC architecture is used to route packets, then the structure is simple, but bandwidth utilization is inefficient due to header and control flit transfers consuming significant resources
Solution Approach 1:
The network architecture is segmented into multiple layers (wide layer and narrow layer) with different packet size capabilities. The wide layer handles full packets including headers and control information, while the narrow layer handles only data payloads. This segmentation allows simultaneous transmission of different packet types without interference, improving bandwidth utilization while maintaining manageable complexity through modular layer design.
Solution Approach 2:
The solution transitions from a single-layer architecture to a multi-layer architecture, adding a vertical dimension to the network structure. By organizing routing resources across multiple layers with different capabilities, the system achieves better bandwidth utilization by allowing parallel transmission paths for different packet types, effectively solving the resource contention problem without excessive complexity.
2Reliability
If header and control flits are transferred through the NOC, then complete packet routing is achieved, but area and power consumption increase significantly
Solution Approach 1:
The patent extracts the header and control information transfers from the data payload transmission path. By separating these functions into the wide layer (which handles complete packets with headers) and the narrow layer (which handles only data), the system achieves complete packet routing while reducing power consumption in the narrow layer since it only needs to handle simpler data transfers without header processing overhead.
3Measurement precision
If more transfer slots are allocated for header and control information, then routing accuracy is maintained, but bandwidth efficiency decreases
Solution Approach 1:
The patent applies local quality by giving different layers different capabilities suited to their specific functions. The wide layer is designed to handle complete packets with headers and control information, while the narrow layer is optimized for high-speed data payload transfer. This localized optimization allows each layer to operate at peak efficiency for its intended purpose, maintaining routing accuracy in the wide layer while maximizing bandwidth efficiency in the narrow layer.
Data Source
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AI summary
An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.