Double-Layer Compound Register System Resisting Power Analysis Attacks
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Solution Overview
Problem
Standard registers in chip hardware devices are vulnerable to power analysis attacks due to varying Hamming Weight (HW) and Hamming Distance (HD) values, leading to information leakage, and existing solutions like Dual-rail Precharge Logic (DPL) registers reduce throughput.
Innovation Solution
A double-layer compound register system comprising a control unit, work register, complementary register, output register, and output complementary register, where the control unit manages the states of these registers to maintain constant HW and HD values, ensuring resistance to power analysis attacks without reducing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Dual-rail Precharge Logic (DPL)-structure register is used to resist power analysis attacks, then security against power analysis attacks is improved, but throughput is reduced to half of the standard register
Solution Approach 1:
The register is divided into four sub-registers (first, second, third, and fourth sub-registers) instead of using a single standard register. This segmentation allows parallel processing of data bits, where the first and second sub-registers process data in one clock cycle while the third and fourth sub-registers handle complementary data, thereby maintaining high throughput while ensuring constant Hamming Weight and Hamming Distance values for power analysis resistance.
Solution Approach 2:
The patent combines multiple sub-registers into a unified DPL-structure register system that operates together to achieve both security and throughput goals. The four sub-registers are merged through controlled data flow and clocking mechanisms, allowing the system to process data at full speed while maintaining constant power consumption characteristics through the coordinated operation of all sub-registers.
2Productivity
If standard register is used, then throughput is maintained at full speed, but Hamming Weight and Hamming Distance values vary causing information leakage through power analysis
Solution Approach 1:
The patent changes the operational parameters of the register by implementing precharge logic that ensures the Hamming Weight (total number of 1s) and Hamming Distance (number of changing bits between clock cycles) remain constant. This is achieved through controlled data routing and inversion operations across the four sub-registers, transforming the variable power consumption of standard registers into constant power consumption while maintaining full throughput capability.
3Reliability
If DPL-structure register processes data sequentially through multiple clock cycles, then power analysis resistance is achieved, but the time required to output data increases
Solution Approach 1:
The patent implements continuous data processing across all four sub-registers simultaneously, eliminating idle clock cycles. While the first sub-register processes data bits 0-3 in one clock cycle, the second sub-register processes inverted data bits 4-7 in parallel, ensuring that every clock cycle contributes to productive data output. This continuous operation maintains full throughput while the constant power consumption characteristics provide power analysis resistance.
Solution Approach 2:
The precharge logic is activated in advance during the precharge phase of each clock cycle, preparing the sub-registers for the next data processing operation. This preliminary action ensures that data is ready for immediate processing without waiting for sequential operations to complete, thereby reducing data output time while maintaining the constant Hamming Weight and Hamming Distance properties needed for power analysis resistance.
Data Source
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AI summary
With the double-layer compound register system and method for resisting power analysis, in the first half of the clock cycle, the control unit may enable the work register and the complementary register, the values of which are complementary, to work and enable the output register and the output complementary register, the values of which are complementary, to reset. In the second half of the clock cycle, the control unit may enable the output register and the output complementary register, the values of which are complementary, to work, and enable the work register and the complementary register, the values of which are complementary, to reset. Therefore, HD values and the HW values of the system in the work state may be constant. The system not only may resist the power analysis attacks, but also may reduce the clock cycle for outputting a group of data to one clock cycle. Therefore, the throughput of the whole chip may be enhanced. Components used by the double-layer compound register system in embodiments of the present disclosure may satisfy requirements of the standard circuit component database, and may have good compatibility, such as may be compatible with the chip.