Double Layered Gate Electrode for Thin Film Transistor Doping Control
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Solution Overview
Problem
Conventional methods for manufacturing thin film transistor array panels face challenges in controlling doping concentration and applying excimer laser annealing effectively, particularly in the GOLDD structure, which affects the reliability and characteristics of thin film transistors.
Innovation Solution
A method involving the formation of a semiconductor layer with a double layered metal structure, where the second metal layer acts as a doping mask to create lightly doped drain regions with lower impurity concentration, and excimer laser annealing is used to activate impurities, enhancing the reliability of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GOLDD structure manufacturing method is used, then high reliability and reduced off current are achieved, but doping concentration control becomes difficult and excimer laser annealing cannot be applied
Solution Approach 1:
The gate electrode is divided into two distinct metal layers (first metal layer and second metal layer) with different widths. The second metal layer extends wider than the first metal layer, creating a stepped structure. This segmentation allows the second metal layer to serve as an effective doping mask for forming LDD regions with controlled doping concentrations, while the first metal layer maintains the electrical connection. The segmented structure enables precise control over doping regions without compromising TFT reliability.
2Reliability
If conventional GOLDD structure manufacturing method is used, then high reliability is achieved, but excimer laser annealing process cannot be applied
Solution Approach 1:
The gate electrode is segmented into two metal layers with different lateral extents. The first metal layer has a narrower width while the second metal layer extends wider, creating a stepped configuration. This segmentation enables the structure to maintain high reliability through proper doping control while simultaneously allowing excimer laser annealing to be applied for activating dopants and forming stable LDD regions.
3Manufacturing precision
If double layered gate electrode structure is formed, then doping concentration control and excimer laser annealing are enabled, but device complexity increases
Solution Approach 1:
The doping mask function and gate electrode function are merged into a single integrated structure consisting of two metal layers. The second metal layer serves dual purposes: as part of the gate electrode for electrical connection and as a doping mask for defining LDD regions. This merging eliminates the need for separate doping mask layers and complex alignment processes, thereby enabling precise doping concentration control while avoiding significant increases in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the lightly doped drain regions, improving the reliability and characteristics of thin film transistors by simplifying the manufacturing process and reducing costs, while maintaining high on-current and reducing off-current.
Implementation Method 1
activating conductive impurities of the semiconductor layer by using laser annealing
Implementation Method 2
applying excimer laser annealing process
Data Source
AI summary
A method of manufacturing a thin film transistor array panel is provided, which includes forming a semiconductor layer of poly silicon, forming a gate insulating layer on the semiconductor layer, forming a conductive layer including a first metal layer and a second metal layer formed on the first metal layer, depositing and forming a photoresist pattern on the first and the second metal layer, forming a gate electrode by etching the conductive layer, wherein the gate electrode includes a double layered structure including the first metal layers having a narrower width than a width of the second metal layer, forming a source region and a drain region in the semiconductor layer by doping conductive impurities, ashing the photoresist pattern to expose a portion of the second metal, etching the exposed portion of the second metal layer, removing the photoresist pattern, and forming lightly doped drain regions having a lower concentration compared to the source region and the drain region by using the gate electrode as a doping mask.