Double-Layered Insulating Structure for Gate Contact Plugs
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and improving production yield and electrical properties, particularly in the design of memory cells and interlayer insulating structures.
Innovation Solution
The semiconductor device incorporates a double-layered insulating structure with a first insulating layer and a second insulating layer of different materials, surrounding gate contact plugs and gate electrodes, which enhances electrical isolation and reduces etching difficulties during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer insulating structure is used around gate contact plugs, then the device structure is simpler, but etching difficulties increase and unwanted connections occur during manufacturing
Solution Approach 1:
The insulating structure is divided into two separate layers: a first insulating layer and a second insulating layer. This segmentation allows each layer to perform specific functions - the first layer provides base insulation while the second layer prevents unwanted connections during etching, thereby resolving the etching difficulties without requiring excessive structural complexity
Solution Approach 2:
The first insulating layer acts as an intermediary between the gate contact plug and the second insulating layer. This intermediate layer facilitates the etching process by providing a controlled interface that prevents direct unwanted connections, making the manufacturing process easier while maintaining manageable device complexity
2Quantity of substance
If gate electrodes extend by different lengths in the second direction, then data storage capacity increases, but production yield decreases due to unwanted connections
Solution Approach 1:
The insulating structure is applied locally around gate contact plugs with different lengths corresponding to gate electrodes of different lengths. This localized insulation ensures that each gate electrode maintains its specific length for data storage capacity while preventing unwanted connections, thereby improving production yield without sacrificing storage capacity
Solution Approach 2:
The insulating structure parameters (material composition, thickness) are optimized to prevent unwanted connections while accommodating gate electrodes of varying lengths. By adjusting these parameters, the device achieves both high data storage capacity through extended gate electrodes and high production yield through effective connection prevention
3Reliability
If gate contact plugs penetrate through multiple gate electrodes, then electrical connectivity improves, but reliability decreases due to unwanted connections
Solution Approach 1:
The first and second insulating layers serve as intermediary barriers between the gate contact plug and surrounding gate electrodes. These intermediary layers maintain reliable electrical connectivity to the intended gate electrode while blocking unwanted connections to adjacent electrodes, thereby resolving the contradiction between connectivity and harmful factors
4Reliability
If a double-layered insulating structure with different materials is used, then unwanted connections are prevented, but device complexity increases
Solution Approach 1:
The insulating structure uses composite materials with the first insulating layer and second insulating layer made of different materials. This composite approach provides superior electrical isolation and prevents unwanted connections through material properties, while the layered configuration keeps the overall structural complexity manageable through systematic design
Data Source
AI summary
A semiconductor device includes a first semiconductor structure, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a substrate having first and second regions, gate electrodes spaced apart from each other on the first region, extending by different lengths and respectively including a pad region having an upper surface exposed upwardly, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes, gate contact plugs penetrating through the pad region of each of the gate electrodes and extending into the first semiconductor structure, and an insulating structure alternating with the interlayer insulating layers below each of the pad regions and surrounding the gate contact plugs. The insulating structure includes a first insulating layer and a second insulating layer surrounding at least a portion of the first insulating layer and including a material different from any of the first insulating layer.