Double-Layered Metal Contacts for DRAM Integration Density
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Solution Overview
Problem
The reduction in size of DRAM devices to achieve high integration density leads to decreased cell capacitance, increased parasitic capacitance, and challenges in forming accurate line patterns, resulting in electrical shortages and reduced integration density due to increased metal contact hole depths and sloped sidewalls.
Innovation Solution
A semiconductor device with a double-layered metal contact structure, where upper and lower metal layers are connected through metal contact plugs, forming a peripheral circuit such as a sense amplifier or sub-word line driver, with optimized design rules to increase pattern density and reduce electrical shortages by minimizing contact plug spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of cell capacitors is increased to obtain sufficient cell capacitance, then cell capacitance is improved, but the step height between cell array region and peripheral circuit region increases, increasing burden on etch process
Solution Approach 1:
The patent introduces a dual-layer metal contact structure (first metal contact plug and second metal contact plug at different depths) to resolve the etching difficulty caused by large step heights. Instead of forming a single deep contact hole across the entire height difference, the contact path is divided into two segments at different vertical levels, with each etch process dealing with a smaller depth range, thereby improving etch process margin while maintaining sufficient cell capacitance.
2Reliability
If distances between metal contact holes are increased to prevent electrical shortages, then electrical shortage probability is reduced, but integration density is degraded
Solution Approach 1:
The patent utilizes the vertical dimension by forming contact plugs at two different depth levels (first metal contact plug and second metal contact plug). This allows horizontal spacing between contacts to be reduced while maintaining reliability, as the vertical separation provides additional isolation path. Consequently, integration density is improved while electrical shortage probability remains low.
3Device complexity
If single patterning technology is used to form line patterns in peripheral circuit region, then process complexity is reduced, but accurate formation of fine line patterns becomes difficult as design rule is reduced
Solution Approach 1:
The patent applies double patterning technology to form the first peripheral interconnection pattern and second peripheral interconnection pattern separately. This segmentation of the patterning process enables accurate formation of fine line patterns even at reduced design rules, as each patterning step works within a larger effective pitch, thereby achieving the required manufacturing precision despite increased process complexity.
Data Source
AI summary
Semiconductor devices are provided. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, first and second conductive line extending onto the semiconductor substrate to constitute a peripheral circuit, a first interlayer insulation layer on the first and second conductive lines, a first peripheral interconnection pattern on the first interlayer insulation layer of the peripheral region, a first contact plug disposed in the first interlayer insulation layer, second peripheral interconnection patterns on the second interlayer insulation layer of the peripheral region, a second contact plug disposed in the second interlayer insulation layer to electrically connect the first peripheral interconnection pattern to one of the second peripheral interconnection patterns, and a third contact plug penetrating the first and second interlayer insulation layers to electrically connect the second conductive line to another one of the second peripheral interconnection patterns.