Double Lockout Programming for Non-Volatile Memory Cells
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Solution Overview
Problem
Non-volatile memory devices face challenges in accurately verifying the threshold voltage of memory cells, leading to issues such as charge gains and losses after verification, resulting in under or over-programming and memory cells moving out of target data states.
Innovation Solution
Implementing a double lockout programming process with temporary and permanent lockout stages, where memory cells are temporarily locked out from programming after initial verification, allowing for a hidden delay before final verification, enabling detection of charge gains or losses and adjusting programming rates to ensure accurate data states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are verified immediately after programming, then programming speed is improved, but charge gains and losses occur leading to programming accuracy degradation
Solution Approach 1:
The patent applies preliminary action by performing a first verification at a first verify level immediately after programming to quickly assess programming status, then implementing a temporary lockout before a second verification at a second verify level to detect charge fluctuations. This preliminary first verification maintains speed while the subsequent delayed verification ensures accuracy.
Solution Approach 2:
The verification process is segmented into two distinct stages: a first verification at a first verify level followed by a second verification at a second verify level after a temporary lockout. This segmentation allows the system to balance speed and accuracy by performing quick initial verification and then more thorough delayed verification for cells that require it.
2Manufacturing precision
If a delay is introduced between programming and verification to detect charge fluctuations, then programming accuracy is improved, but program time increases
Solution Approach 1:
The patent performs a preliminary first verification immediately after programming before implementing the delay, allowing most cells to be quickly verified without delay. Only cells that fail the first verification or require additional verification undergo the temporary lockout and delayed second verification, thus minimizing overall time loss while maintaining accuracy.
Solution Approach 2:
The temporary lockout and delayed second verification are applied selectively rather than universally. Only memory cells that require additional verification undergo the time-consuming delayed verification process, while other cells complete programming quickly, thus reducing the average program time loss while ensuring accuracy for cells that need it.
3Manufacturing precision
If memory cells are locked out from programming after initial verification, then programming accuracy is improved through delayed verification, but device complexity increases
Solution Approach 1:
The control circuit is segmented into distinct functional blocks: a first verify circuit for initial verification, a lockout circuit for temporary lockout management, and a second verify circuit for delayed verification. This segmentation organizes the complexity into manageable, modular components that can be independently controlled and managed.
Solution Approach 2:
The lockout circuit is configured to automatically implement temporary lockout based on predetermined criteria from the first verification results, eliminating the need for complex real-time decision-making logic. This preliminary configuration of lockout conditions simplifies the control circuit design while maintaining accurate programming verification.
Data Source
AI summary
A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.